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In this paper, various approaches to extend scalability of Hafnium-based dielectrics are reported. Among the three crystal phases of HfO2 (monoclinic, cubic and tetragonal), the tetragonal phase has been reported to have the highest dielectric constant. Tetragonal phase stabilization by crystallizing the thin HfO2 using a metal capping layer and by adding zirconium is demonstrated. The microstructure, morphology, optical properties and impurities of HfxZr1-xO2 dielectrics (for 0<x<1) are discussed. Subtle but important modification to high-k / Si interface characteristics resulting from addition of Zr into HfO2 is reported. To further boost the dielectric constant of hafnium-based dielectrics, incorporation of TiO2, which has been reported to have high dielectric constant, is explored. HfxZr1-xO2/TiO2 bilayer films were fabricated. 30 Å TiO2 films were deposited on a 5, 8, 12 or 15 Å HfxZr1-xO2 underlayer to determine the minimum thickness needed to maintain good thermal stability with Si substrate. CV and IV results indicated that 12-15 Å is the optimal thickness range for the HfxZr1-xO2 underlayer. A dielectric constant as high as 150 for TiO2 layer is extracted from TiO2 thickness series deposited on12 Å HfxZr1-xO2 underlayer. In addition to increasing the k-value of Hafnium-based dielectrics, it is important that the threshold voltage of these high-k devices is low. Here we report the use of thin Al2O3 capping layers to modulate PMOS threshold voltages. About 100 mV reduction in threshold voltage is achieved by capping HfO2 with a 5Å Al2O3 film. Finally, dielectric scaling by modifying the Si/high-k interfacial layer is attempted. Nitrogen incorporation into HfxZr1-xO2 is shown to be a simple and effective method to lower the capacitance equivalent thickness (CET) of Hafnium-based dielectrics.
A fast way to monitor the quality of high-k dielectric layers is wet etching, either monitored by Open Circuit Potential analysis or by Scanning Electron Microscopy. Defect densities in the order of 1.109 defects/cm2 are observed for as-deposited HfO2 layers. It is assumed that the mechanism for wet chemical defect observation is either due to crystallization and/or due to an oxygen deficient HfO2 layer resulting in Si/SiO up-diffusion upon thermal treatment. However, after appropriate post deposition annealing wet etch defect free layers can be prepared.
Single wafer amorphous silicon deposition was characterized through process modeling and film characterization for application in semiconductor production. DOE methodology was used to determine the main deposition parameters, and the responses were limited to device production requirement properties of surface roughness, deposition rate and degree of crystallinity of the as-deposited film. The data trends and models show that deposition temperature and silane flow are the main factors. Increasing either or both factor increases the deposition rate and the surface roughness. The surface morphology, evaluated by AFM, SEM and TEM, was found to be rougher at extreme growth conditions than the poly crystalline film formed after anneal. The as-deposited surface morphology was not a result of pre-anneal crystal formations as determined by TEM cross sections of samples before and after anneal. Lack of crystalinity is important for impurity diffusion considerations. Device application of the single wafer a-Si process will be a compromise between growth rate (and associated throughput) and surface roughness that can be tolerated.
PZT ferroelectric capacitors are commonly fabricated using Pt electrodes. Crystallization in an oxygen ambient of sol-gel deposited PZT films is influenced by the nature of the adhesion layer used for the Pt electrode. Here we report results of the TEM investigation of the microstructures of PZT crystallized on Pt/Ti and Pt/TiO2 substrates. PZT films on either substrate show a two-phase microstructure consisting of larger perovskite grains and finegrained (<3nm) pyrochlore matrix. The perovskite grains are dense, free of any porosity and HRTEM shows the observed domains to be 90° <101> twins. EDS spectra detect a lower Pb/Ti ratio for the pyrochlore matrix compared to the perovskite grains. Differences between the two substrates consist of the perovskite to pyrochlore ratio and more importantly the perovskite grain size.
High fluence ion implantation of N (1x1018/cm2 at 150 keV) has been used to form buried nitride layers in (110) silicon. After annealing at 1200 C for 5 hrs. a continuous, polycrystalline alpha-Si,N- layer (200 nm thick) is observed beneath a surface silicon film 306 nm thick. The upper Si/Si3N4 interface appears to be more abrupt than that observed in (100) silicon with minimal dendritic intergrowth and no evidence for microtwinning in the silicon. Furthermore, a band of nitride precipitates can be detected 500 nm below the continuous nitride layer. These nitride precipitates grow semi-coherently within the silicon with no observable strain or misfit dislocations within the silicon. The nitride precipitates are internally faulted to accomodate the 10% lattice mismatch in the (0001) nitride direction. Short term anneals reveal that the precipitates have fully crystallized within 10 min. at 1200 C while the continuous nitride layer is still amorphous.
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