The ferroelectricity in fluorite-structure oxides such as hafnia and zirconia has attracted increasing interest since 2011. They have various advantages such as Si-based complementary metal oxide semiconductor-compatibility, matured deposition techniques, a low dielectric constant and the resulting decreased depolarization field, and stronger resistance to hydrogen annealing. However, the wake-up effect, imprint, and insufficient endurance are remaining reliability issues. Therefore, this paper reviews two major aspects: the advantages of fluorite-structure ferroelectrics for memory applications are reviewed from a material's point of view, and the critical issues of wake-up effect and insufficient endurance are examined, and potential solutions are subsequently discussed.

Ferroelectrics are promising for nonvolatile memories. However, the difficulty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.

Si is a promising anode material for Li storage due to its high theoretical specific capacity surpassing 4200 Ah/kg. Si based anodes exhibit an extreme instability upon electrochemical incorporation of Li given the accompanied large volume expansion of about 400%. We show innovative anode assemblies composed of a forest of free standing Si nanowires conformally integrated on carbon meshes. The morphology of silicon nanowires allows a volume expansion and compression lowering strain incorporation. In this paper, we demonstrate the utilization of SiNW grown on top of a current collector made of a carbon fiber network. This leads to an increase of stability of Si with a remaining effective capacitance above 2000 Ah/kg(Si) after 225 full charge/discharge cycles. This is significantly better compared to previous results shown in literature. The anodes are fabricated by a simple and inexpensive method promising for a transfer into industrial integration.

Reconfigurable nanowire transistors provide the operation of unipolar p-type and n-type FETs freely selectable within a single device. The enhanced functionality is enabled by controlling the currents through two individually gated Schottky junctions. Here we analyze the impact of the Schottky barrier height on the symmetry of Silicon nanowire RFET transfer characteristics and their performance within circuits. Prospective simulations are carried out, indicating that germanium nanowire based RFETs of the same dimensions will show a distinctly increased performance, making them a promising material solution for future reconfigurable electronics.

An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at < 200 W/m2 irradiation; 0.99 power factor, 87% efficiency and 0.088 distortion factor for dc supplies; 1 ns synchronization resolution via Ethernet; database accelerators allowing 85% energy savings for servers; adaptive software yielding energy reduction of 73% for e-Commerce applications; processors and corresponding data links with 40% and 70% energy savings, respectively, by adaption of clock frequency and supply voltage in less than 20 ns; clock generator chip with tunable frequency from 83-666 MHz and 0.62-1.6 mW dc power; 90 Gb/s on-chip link over 6 mm and efficiency of 174 fJ/mm; dynamic biasing system doubling efficiency in power amplifiers; 60 GHz BiCMOS frontends with dc power to bandwidth ratio of 0.17 mW/MHz; driver assistance systems reducing energy consumption by 10% in cars

This article reviews recent progress in understanding the resistive switching (RS) behavior and improvements in device performance of RS metal oxide (MO) thin-film systems and devices. The diverse RS MO materials are classified according to their switching mechanisms and characteristics. For each category, some representative materials are selected, and their characteristics are discussed. In addition, other factors such as the device structure, which also plays a crucial role in determining the device properties, are discussed as well. When applied in a real circuit (e.g., in a crossbar structure), there are device features/characteristics that need to be considered, including the bias polarity for switching, the current-voltage relationship, reliability, and scaling issues. Since nonvolatile RS in many MO materials is primarily associated with localized conduction channels, understanding the nature and the dynamic change of the current path structure is crucial and therefore is reviewed at length here. Guidelines for the choice of materials and access devices and their fabrication methods will also be provided. Finally, this review concludes with the outlook and challenges of MO-based resistance change devices for semiconductor memories.

Ferroelectric random access memories (FeRAMs) are new types of memories especially suitable for mobile applications due to their unique properties such as nonvolatility, small DRAM - like cell size, fast read and write as well as low voltage / low power behavior. Although standard CMOS processes can be used for frontend and backend / metallization processes, FeRAM technology development has to overcome major challenges due to new materials used for capacitor formation. In this paper, advantages and disadvantages of different ferroelectric materials and major development issues for high density applications are discussed. Results of a 0.5μm ferroelectric process using SrBi2Ta2O9 (SBT) as ferroelectric layer, Pt as electrode material, and 2-layer tungsten / aluminum metallization are discussed.