We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.

A statistically designed experiment was run to optimize the deposition of PECVD SiN on GaAs substrates. Five deposition parameters were varied: RF power, temperature, pressure, plasma frequency, and ammonia/silane ratio. Four film properties were used to evaluate the quality of the nitride: the fraction of hydrogen bound to nitrogen atoms, the index of refraction (and its uniformity), thickness uniformity, and stress. From the screening phase of the experiment, it was determined that only the plasma frequency and ammonia/silane ratio influenced the quality of the nitride film. High frequency deposition was preferable to low frequency deposition since it resulted in lower film stress. The results of the optimization phase showed that SiN films with near‐zero stress, low N‐H bond density and good index of refraction could be obtained by deposition at a very low ammonia/silane ratio.

An Eaton Nova Rapid Optical Annealer (ROA 400) has been used to activate n and n+ Si implants for use in power and low noise FET structures for GaAs MMIC's. PECVD SiN capped 3" SI GaAs wafers were annealed at temperatures ranging from 800 to 970 °C for times ranging from 0 (transient light pulse) to 20 sec. Doping profiles were determined using a Polaron concentration profiler; FATFET's were used for measuring drift mobility; and short gate (l.0μm gate length) FET's were fabricated to establish activation uniformity and to determine d.c. and r.f. performance. Results have indicated peak implant activation as high as 90% and electron mobilities of up to 4700cm2/V-sec for carrier concentrations of 1.3×1017/cm3 – results comparable to conventional furnace annealing. The most significant improvement of optical annealing comes in device uniformity. Saturated current uniformities of < ±3% have been achieved over 3" wafers with excellent reproducibility from wafer to wafer. Power FET structures with zero bias gm of 120mS/mm with uniformities of <±5mS/mm have been measured. R.f. measurements on these devices yielded output powers of >500mW/mm with power added efficiencies as high as 35%.