Crystal distortions modify the propagation of X-rays in single crystal materials, and X-ray topography can be used to record these modifications on a film thus providing images of the distributions and nature of defects, dislocations, strains, precipitates, etc. in semiconductors. Small variations of contrast, which often need to be analysed can be rendered invisible. Furthermore, artefacts in the films must be removed. This study examines the use of advanced image analysis techniques applied to a selection of X-ray topographs in section transmission mode: (i) the automated counting of oxygen-related precipitates and (ii) the enhancement of Pendellösung fringes. The technique also succeeds in removing unwanted features in the original x-ray topographs such as vertical streaking due to collimating slit phase contrast and strain features near the surface due to the presence of integrated circuit process strains.

The Epitaxial Lateral Overgrowth (ELO) of GaN on Al2O3 using a SiO2 mask with different fill factors (ratio of stripe opening width to stripe period) is examined with White Beam Synchrotron X-ray Topography (WBSXT) and X-ray rocking curve analysis. The sapphire substrate was identified with a dislocation density of the order of ~106cm-2. WBSXT in both transmission and back reflection mode is used to image the ELO GaN and confirms that crystal planes in the lateral overgrown part (wing) are tilted, and that the wing tilt increases as the fill factor increases. X-ray rocking curve and WBSXT measurements confirm the same wing tilt tendency as the fill factor changes. The WBSXT method provides a measure of the maximum wing tilt, while the X-ray rocking curve method gives the average wing tilt. The average wing tilt reaches about 1602 arcsec at a fill factor of 0.625, but the maximum wing tilts can reach values as large as 2372 arcsec when the fill factor is only 0.571. This study shows that WBSXT is an effective method in dislocation and wing tilt determination for the GaN on Al2O3 ELO epilayer system or indeed for similar systems. The tilted wings induce a slightly lower compressive stress in the coalesced region of the GaN epilayer.

Solder based flip-chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-chip packaging techniques used for microprocessor applications. However, mechanicalstresses induced by the flip-chip process can impact adversely on the reliability of production.

White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microprocessors due to the lead-tin solder bump process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow process are ingood agreement with the SXRT results.

The objective of this work is to study defect occurrence and appearance in thick sublimation epitaxial layers grown on top of LPE layers with different thickness and substrates with reduced micropipe density. Data from growth on C-terminated surfaces are also presented. The results were analyzed with the aid of optical microscopy, SEM images, HRXRD and synchrotron white beam X-ray topography. A pronounced effect of the LPE (buffer) layer surface roughness on formation of dislocations and micropipes is observed in the sublimation epitaxy layers. While with increasing the thickness of the buffer layer the efficiency of the micropipe reduction increases, the structure quality of the top sublimation epilayer degrades. LPE layers with a thickness of 0.1 μm appear to be the best compromise.

Synchrotron white beam x-ray topography techniques, in section and large-area transmission modes, have been applied to the evaluation of ELOG GaN on A12O3. Using the openings in 100 nm thick SiO2 windows, a new GaN growth took place, which resulted in typical overgrowth thicknesses of 6.8 μm. Measurements on the recorded Laue patterns indicate that the misorientation of GaN with respect to the sapphire substrate (excluding a 30° rotation between them) varies considerably along various crystalline directions, reaching a maximum of a ∼0.66° rotation of the (0001) plane about the [01•1] axis. This is ∼3% smaller than the misorientation measured in the non-ELOG reference, which reached a maximum of 0.68°. This misorientation varies measurably as the stripe or window dimensions are changed. The quality of the ELOG epilayers is improved when compared to the non- ELOG samples, though some local deviations from lattice coherence were observed. Long range and large-scale (order of 100 μm long) strain structures were observed in all multi quantum well epilayers.

Synchrotron x-ray topographs of GaAs epitaxial lateral overgrowth (ELO) samples are made both in transmission and reflection geometries. The topographs show that the bending of the ELO layers is visible in most geometries. A simulation of the topographic images is implemented taking into account only the orientational contrast. Simulated back reflection section topographs are in good agreement with the experimental ones. The shape of the lattice planes in an ELO layer is calculated using the simulation data and compared to the measured surface profile of the same ELO stripe.

Thermal processing steps in the production of packaged integrated circuits can lead to thermomechanical stresses. Additionally, the process of bonding wires to contact pads can lead to strain fields attributable to these. Synchrotron x-ray topography has been applied to packaged EEPROM Si ICs in order to produce maps of the strain fields induced by such processing steps. This technique allows for depth-resolved mapping with resolutions currently in the region of 5–10 μm throughout the entire mapping volume.

The continued decrease in critical dimensions and increasing integration levels in Si CMOS technology is imposing ever tighter constraints on quality control parameters for the IC manufacturing industry. One very important issue is the need to ensure a uniform, high quality Si substrate, i.e. minimise defect/dislocation densities and eliminate strain distributions in the starting wafer material. A comprehensive Synchrotron X-Ray Topography (SXRT) study was applied to commercially supplied 200mm diameter Si wafers. These wafers, which all included a surface Si epilayer growth were supplied from manufacturers from around the globe. The study revealed not only differences in the overall quality of the wafers, but also differences in the quality of the individual Silicon epilayers and substrates. In all wafers the substrate quality varied dramatically with position across the wafer, as measured by the distribution of oxygen precipitates and stacking faults in the wafer. This distribution also varied significantly from manufacturer to manufacturer. The strain fields induced by the growth of lightly doped Si epilayers were also observed to qualitatively vary with location on a wafer, together with (as expected) thickness of the epilayers. The results clearly indicate that optimal quality control for such commercial wafers has not yet been achieved.

The use of some specific compound semiconductors in the fabrication of high energy X-ray detectors shows significant potential for X-ray astrophysics space missions. We are currently investigating three high purity crystals - CdZnTe, GaAs and TlBr - as the basis for future hard X-ray detectors (above 10 keV). In this paper we present the first results on CdZnTe and GaAs based detectors and evaluate the factors currently still constraining the performance.

Energy resolutions (FWHM) of 0.9 keV and 1.1 keV at 14 keV and 60 keV, respectively, have been obtained with an epitaxial GaAs detector, while 0.7 keV and 1.5 keV FWHM were measured at the same energies with a CdZnTe detector. Based on these results it is clear, that the next generation of X-ray astrophysics missions now in the planning phase may well consider extending the photon energy range up to ∼100 keV by use of efficient detectors with reasonable spectroscopic capabilities.

Large area transmission and section topographs of semi-insulating gallium arsenide wafers grown by the gradient freeze technique are made with synchrotron radiation at HASYLAB in Hamburg and at ESRF in Grenoble. Several high-resolution images including stereo pairs are obtained on the same film at a time. A typical dislocation line is an arc of a circle which starts from one surface and ends at the same surface. From the disappearance of the dislocation image and using the g · b = 0 criterion it is concluded that the Burgers vector b of the most common dislocations is parallel to 〈110〉. Rather large volumes of the wafer are dislocation-free. Section topographs of epitaxial wafers show defects and strain fields at the interface between an n-type substrate and the epitaxial layers grown by chemical vapor deposition. The results are compared with those obtained from detector performance measurements.

The electrical and charge collection properties of a semiconductor detector play an important role in a spectrometer's final performance. However, the studies of these properties often concentrate on only a few samples. In this work over 100 CdZnTe detectors from 12 different growth boules were characterized with one of the following test methods. The composition uniformity was evaluated with low temperature photoluminescence (PL) measurements. From the current-voltage characteristics the differences in CdZnTe detector resistivities were investigated. Charge collection properties, μτ-products, and energy resolutions were characterized with spectroscopic methods using an alpha and isotopic sources. A wide selection of test results are presented indicating the variety of CdZnTe material.

For high-power device applications SiC has better physical and electronic properties than the traditional semiconductor materials Si and GaAs. In this work, structural defects of 4H SiC wafers have been studied and partly compared with results from a previous study of 6H material. Optical microscopy, scanning electron microscopy, high-resolution X-ray diffraction and synchrotron X-ray topography were used for structural studies of 4H SiC.Optical micrographs show micropipes and larger specific defects - tubes and cracks. X-ray rocking curve peaks are broad and split revealing the mosaicity of the material. Synchrotron X-ray topographs show areas having a large number of defects, images of cracks and micropipes, and misorientated regions close to the micropipes.

Recently observations that high-dose Ge implantations into Si substrates caused the n-type carrier concentration to increase were attributed to residual structural defects after activation annealing [7,12]. However, co-implantation of an n-type impurity is another possibility. The origin of this excess donor concentration has been studied in this work. The possibilities of residual defects versus implantation of impurities have been investigated using two different implanters and materials analysis. Comparison of data from different implanters showed that the concentration of excess donors was sensitive to the implanter configuration. Furthermore, transmission electron microscopy (TEM), Rutherford backscattering channeling (RBS-C), and spreading resistance profiling (SRP) data showed that the excess donor effect was related to impurities rather than residual defects. Secondary-ion mass spectroscopy (SIMS) and SRP measurements confirmed that impurities such as 75As ions were present after implants. This impurity easily explains the excess donor concentration when 75Ge implants are performed into silicon wafers doped with phosphorous.

Praseodymium dioxide (PrO2) -doped In0.69Ga0.31As0.67P0.33 layers are grown on semiinsulating In P substrates with liquid-phase epitaxy. The PrO2 doping of the growth solution varies from 0 to 0.32 wt %. The quaternary In0.69Ga0.31As0.67P0.33 layer composition determined with two-crystal X-ray diffraction and photoreflectance is found to be independent of the PrO2 concentration in the melt. The photoluminescence spectra measured at 12 K show both exciton and donor-acceptor peaks, the magnitudes of which depend on the PrO2 doping. The carrier concentration of the n-type quaternary layer decreases and the mobility increases with increasing PrO2 concentration and reaches the values of 8.3.1015 cm−3 and 7300 cm2/Vs, respectively, at about 0.1 wt% at 77 K. The experiments show that PrO2 has an impurity gettering effect in the growth process.

The gettering effectiveness of various backside gettered polysilicon, silicon nitride, or poly + nitride film structures on n-type (100) Czochralski silicon wafers from a single ingot during simulated complementary-metal-oxide-semiconductor process cycles has been investigated by synchrotron section topography, breakdown voltage of 25-nm gate oxide, and minority carrier lifetime measurements. Interfacial structure was studied by cross-section transmission electron microscopy. Our studies show that for successful implementation of thin film backside gettering, good control of interactions between intrinsic gettering and thin film backside gettering during device processing cycles is critical. Thin film deposition generally increases oxygen precipitation. No extended defects propagate toward the bulk silicon. The structural and electrical quality of a denuded zone is found important. The best device yield (90%) is observed from the middle section wafers (with a 2 μm thick polysilicon backsurface coverage) which develop no recognizable bulk precipitates and stacking faults after the complete thermal cycles.

Effects of post-well drive intrinsic gettering (PWIG) upon the integrity of thin gate oxide in Cz Si wafers with carbon levels, Cs, ranged from 0.2 - ∼ 4 ppma were investigated. A 10 nm thick gate oxide capacitor was used to study its time-dependent breakdown characteristics and minority carrier lifetime. Our data have shown that PWIG cycles and/or carbon impurity affect both bulk oxygen precipitation and minority carrier lifetime, but not the oxide integrity.

Synchrotron section topography is applied to the study of silicon wafers pulled out froma simulated advanced CMOS twin-tub process. Substrates are heavily doped with antimony and phosphorus. For comparison also high-resistivity samples are studied. Prior to epi deposition of arsenic doped layers some wafers are subjected to a three-step intrinsic gettering cycle.

Section topographs show that in the lightly doped samples a denuded zone is formed by the CMOS process itself in contrast with the heavily doped ones in which the intrinsic gettering is needed.

High resolution section topographs are made with synchrotron radiation using exposure times that are 1/1000 or less of those necessary with conventional x-ray sources. The imaging technique is employed to study oxygenrelated defects and their spatial distribution in a large number of annealed p-type (100) Czochralski silicon wafers. A two-step annealing in nitrogen consisted of a nucleation cycle at 800 °C and at 825 °C for 20 h followed by a denuding cycle at 1100 °C for 6 h. Denuded zones measuring from zero to 100 μm are seen in the synchrotron section topographs made after oxidation of the wafers at 1100 °C for 2 h. The denuded zone formation is found to depend strongly on the part of the crystal from which the wafer is cut. The wafers have the same interstitial oxygen concentration but different carbon concentrations. Large spatial variations up to 100 μm of the denuded zone width are observed in some wafers. Synchrotron section topographs of the wafers in which CMOS devices were fabricated showed a denuded zone only if the wafers were thremally annealed before the IC process.