In future technology nodes, 22nm and below, carbon nanotubes (CNTs) may provide a viable alternative to Cu as an interconnect material. CNTs exhibit a current carrying capacity (up to 109 A/cm2), whilst also providing a significantly higher thermal conductivity (SWCNT ~ 5000 WmK) over Copper (106 A/cm2 and ~400WmK). However, exploiting such properties of CNTs in small vias is a challenging endeavor. In reality, to outperform Cu in terms of a reduction in via resistance alone, densities in the order of 1013 CNTs/cm2 are required. At present, conventional thermal CVD of carbon nanotubes is carried out at temperatures far in excess of CMOS temperature limits (400 C). Furthermore, high density CNT bundles are most commonly grown on insulating supports such as Al2O3 and SiO2 as they can effectively stabilize metallic nanoparticles at elevated temperatures but this limits their application in electronic devices. To circumvent these obstacles we employ a remote microwave plasma to grow high density CNTs at a temperature of 400 C on conductive underlayers such as TiN. We identify some critical factors important for high-quality CNTs at low temperatures such as control over the catalyst to underlayer interaction and plasma growth environment while presenting a fully CMOS compatible carbon nanotube synthesis approach

Because of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.

We investigate the structural, optical and electrical properties of single-layer graphene exposed to oxygen plasma treatment. We find that the pristine semimetallic behavior of graphene disappears upon plasma treatment, in favour of the opening of a bandgap and the featuring of semiconducting properties. The metal-to-semiconductor transition observed appears to be dependent on the plasma treatment time. The semiconducting behavior is also confirmed by photoluminescence measurements. The opening of a bandgap in graphene is explained in terms of graphene surface functionalization with oxygen atoms, bonded as epoxy groups. Ab initio calculations of the density of states show more details about the oxygen–graphene interaction and its effects on the graphene optoelectronic properties, predicting no states near the Fermi level at increasing epoxy group density. The structural changes are also monitored by Raman spectroscopy, showing the progressive evolution of the sp2 character of pristine graphene to sp3, due to the lattice decoration with out-of-plane epoxy groups.

High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface. Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

Semiconductor nanowires are attractive nano- building blocks for microelectronics. However, the requirements for their manufacturing and application in the microelectronics industry are very demanding. Beyond compatibility with Si technology, full control on the characteristics of the grown wires (diameter, location, crystallinity, etc..), homogeneity on wafer –scale and reproducibility are essential. In this study we review critically important challenges for a controlled process of In –mediated growth of Si nanowires. First, we stress the importance of surface type for both particle catalysts and growth substrates. Both selection and preparation of such surfaces have large impact on growth, as they influence the initiation and the driving forces for the VLS growth mechanism. Moreover, wire characteristics such as morphology, crystalline quality and growth orientation appear more difficult to control when growing from particles with sizes below 40-50nm. This limitation arises as a result of both fundamental mechanisms and more specific constrains linked to the In-Si system.

A few perspectives are given for the achievement of a controlled Si nanowire growth in a Si –technology compatible fashion.

The integration of high-density CNT bundles as via interconnects in a CNT/Cu-hybrid BEOL stack is evaluated. CNT via-conduits may greatly improve heat dissipation and as such lower interconnect resistance and improve electromigration resistance. Each carbon shell of the nanotube contributes to electrical and thermal conduction and densities as high as 5×1013 shells per cm2 are estimated necessary. CNT growth processes on BEOL compatible metals are presented with tube densities up to 1012cm−2 and shell densities approaching 1013 cm−2 on blanket substrates. Selective growth of CNT bundles with carbon shell densities around 1012cm−2 is demonstrated with high yield. Ohmic behavior of TiN/CNT/Ti contacts is shown with a CNT via resistivity of 1.2 mΩ cm.

Important material properties of dielectric oxide films fabricated by aqueous chemical solution deposition, such as crystallization, topography, contamination and interfacial layer were evaluated and related to the films' dielectric properties.

Functional ultrathin films (<20 nm thickness) of zirconia, barium zirconate and strontium niobate were deposited. The films were all subjected to the same thermal treatment, based on the high similarity of their precursors' thermal decomposition behavior. The evolution of the films' chemical purity as a function of temperature and the effect of annealing on the interfacial SiO2 layer was studied by grazing angle ATR-FTIR. The films' crystallization behavior was dependent on film thickness and composition as shown by high temperature XRD. C-V characterization of the films demonstrated a k-value in the same order of magnitude as for the ZrO2 reference material. This is lower than the bulk material's value, thus leaving room for further optimization of the current materials or alternatively selection of other material compositions.

Ultrathin lanthanide (Nd, Pr, Eu, Sm) oxide films with functional dielectric properties down to 3.3 nm thickness were deposited by aqueous chemical solution deposition (CSD) onto hydrophilic SiO2/Si substrates. Precursor solutions were prepared from the oxides via an intermediate, solid Ln(III)citrate. A film heat treatment scheme was derived from thermogravimetric analysis of the precursor gels, showing complete decomposition by 600 °C. Crystalline phase formation in the films depended on the lanthanide, annealing temperature, and citric acid content in the precursor. Through variation of the precursor concentration and number of deposited layers, thickness series of uniform films were obtained down to ∼3 nm. The film uniformity was demonstrated both by atomic force microscopy and cross-section transmission electron microscopy. The lanthanide oxide films possessed good dielectric properties. It was concluded that aqueous CSD allows deposition of uniform ultrathin films and may be useful for the evaluation of new high-k candidate materials.

The electrical performance of hafnium silicate (HfSiOx) gate stacks grown by atomic layer deposition (ALD) has been evaluated in capacitors and transistors. First, scaling potential of HfSiOx layers was studied as function of composition and thickness. It is shown that the equivalent oxide thickness scales down with decreasing layer thickness and increasing Hf-content. The gate leakage (at Vfb-1V), however, is mainly determined by the physical layer thickness. For the same equivalent oxide thickness (EOT) target, the lowest leakage is observed for the layers with the highest Hf-content. Leakage values as low as 1x10-3 A/cm2 for an equivalent oxide thickness of 1.3 nm have been obtained. Second, the thermal stability against crystallization of the ALD HfSiOx has been studied and related to their electrical properties. The thermal stability of HfSiOx decreases with increasing Hf-content that necessitates the use of nitridation. The influence of various annealing conditions on the nitrogen incorporation is also studied. Finally, the effect of HfSiOx composition and postdeposition nitridation is discussed on transistor level. TaN metal gate transistor data indicate that nitridation reduces the gate leakage and that Hf-rich HfSiOx layers show the best scaling potential, i.e., highest performance for the lowest gate leakage.

The microstructural and electrical characterizations of RuxTa1-x alloys obtained from Ru-Ta laminates are presented. The films were deposited on SiO2 and HfO2 and capped with TiN to avoid oxidation of the top surface. The alloys were attained by post-anneal thermal treatments in the range of 500-1000 °C in Ar atmosphere. Co-sputtered RuxTa1-x alloys were used as references. In particular, Ru0.4Ta0.6 phase could be obtained when the Ru-Ta laminate was annealed at 1000 °C. The alloying reaction is limited either by the tantalum nitride or oxide formation being the source for Nitrogen the TiN capping used on top of the stack and the Oxygen either the dielectric films or the one stuffing the films after exposure to the atmosphere.

Independent of the Ta content a mid gap work function was obtained. Measured WF's in laminate-obtained alloys and alloys themselves differ from other literature data, where a more n-type like WF are measured, and indicating process dependence. In the present study mid-gap or rather p-type work functions were found, 4.5 eV < WF < 4.9 eV.

Atomic layer deposition (ALD) has been successfully used over the years for the deposition of conformal dielectric layers with precise thickness down to the nanometer scale. Therefore, optimization of the growth behaviour of the dielectric is mandatory. Since ALD is a surface sensitive growth technique, determined by the amount of available reaction sites at the starting surface, the impact of various wet chemical and thermal Si treatments on the HfO2 growth was evaluated. Thin SiO2 starting layers, based on wet chemical processing, were prepared by using a diluted peroxide mixture and an ozone/DI-water treatment. The thermally grown oxides were gradually etched by slowly immersing the oxidized Si substrate into a diluted HF solution, creating a thickness range on a single wafer. Our results demonstrate that the HfO2 deposition is more dependent on the thickness of the SiO2 layer than on the chemistry used to grow the oxide layer. For all studied oxides, two regions can clearly be distinguished. First, a linear relationship between the oxide thickness and the amount of deposited HfO2 is seen. Because chemical oxides tend to grow in islands, this trend can be explained by an increase in density of surface OH groups when the oxide grows thicker. When an ellipsometric thickness of ~0.8 nm is reached, saturation of the HfO2 growth is obtained. We believe that, from this thickness on, the starting surface is completely covered with hydroxyl groups, leaving the HfO2 growth only dependent on the ALD process itself. Since both the wet chemical as the thermal oxides are showing the same trend in HfO2 deposition, it can be stated that surface preparations can be selected solely based on their ease of processing. However, the electrical results show that there may be a difference between the ozone based wet chemical oxides and the etched thermal oxides, since the latter seems to possess slightly more leakage current. The electrical results will be discussed in more detail during the presentation.

The electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO2 Poly-Si/Ti(C)N/SiO2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO2 and Poly-Si/Ti(C)N/HfO2 gate stacks.

A fast way to monitor the quality of high-k dielectric layers is wet etching, either monitored by Open Circuit Potential analysis or by Scanning Electron Microscopy. Defect densities in the order of 1.109 defects/cm2 are observed for as-deposited HfO2 layers. It is assumed that the mechanism for wet chemical defect observation is either due to crystallization and/or due to an oxygen deficient HfO2 layer resulting in Si/SiO up-diffusion upon thermal treatment. However, after appropriate post deposition annealing wet etch defect free layers can be prepared.

It is found that Fe in a ppb level Fe-spiked SC1 solution precipitates in-homogenous. The local high iron concentrations are difficult to rinse, create micro-roughness, and induce weak spots in capacitors. With AFM it has been shown that rings of 3–8 μm are etched in the silicon and that the etch products (silicates) are deposited on one side just outside the ring. The capacitor yield loss induced by this SC1 treatment can not be recovered fully by a subsequent SC2 or dHCL step, while a dHF/dHCl does fully recover the yield and removes the iron and silicate rim.