Planarized surfaces have become key to the success of advanced semiconductor devises/circuits/chips. The planarization, achieved by the use of chemical mechanical means, has enabled the interconnection of ever increasing number of devices and also the use of lower resistivity copper as the interconnect material for such devices. Chemical mechanical planarization (CMIP) has now found application at several different stages of semiconductor chip fabrication and many other microelectronic applications. However, there remain a large number of nuances and effects e.g. pattern, chemical, and pad dependencies and scratching, that need to be carefully studied, evaluated and eliminated if we want to continue to progress in sub 0.1 µm (minimum feature size) regime, where the amounts of material to be removed will be small, surfaces will dominate the performance, and margin of error extremely small and unforgiving. This presentation will discuss the future needs, the CMP variables, the relationship of these variables to CMP behavior and planarity, scratch-free CMP, and size-impact on CMP outcome. A new set of goals will be presented and discussed.