We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=-20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. . We also applied same off state bias annealing at SPC-Si TFT with 20,000 lx light illumination in order to verify the reduction of leakage current of SPC-Si TFT under light illumination. The leakage current of SPC-Si TFT was reduced successfully even under light illumination during off-state bias annealing. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

We have investigated the effects of hydrogen plasma treatment on the hysteresis phenomenon and electrical properties of solid phase crystallized silicon thin film transistors (SPC-Si TFTs) employing alternating magnetic field crystallization (AMFC). We employed H2 plasma treatment on the SPC-Si active layer before SiO2 gate insulator deposition. By increasng the power and time duration of H2 plasma treatment, it was observed that hysteresis phenomenon of SPC-Si TFT was suppressed and electrical properties such as threshold voltage, field effect mobility was improved considerably. This is due to role of hydrogen atom by passivating the defects and grain boundary trap states in SPC-Si film. However, relatively high power and long hydrogen plasma treatment (100W, 5 minutes) could degrade the electrical characteristics of the device. SPC-Si TFT for 100W power of PECVD and 3 minutes with the H2 plasma treatment exhibit the significant improvement of electrical characterics (VTH = - 3.85V, μFE = 21.16cm2/Vs), and a smaller hysteresis phenomenon (∆VTH = -0.30V) which is suitable for high quality AMOLED Display.

We have investigated temperature dependence on the hysteresis phenomenon of SLS poly-Si TFT on a glass substrate, extremely at low temperature (213K). The p-type sequential lataral solidification (SLS) polycrystalline Silicon (poly-Si) TFT was fabricated on glass substrate. As the temperature was reduced, it was observed that hysteresis phenomenon was increased, whereas the hysteresis was suppressed at high temperature. This could be explained by a difference of initially electron and hole trapped charges into gate insulator is much larger in low temperature than in high temperature. And we have verified that drain current was changed with a different previous gate starting voltage even at same bias condition by experimental results due to the hysteresis phenomenon of SLS poly-Si TFT. Hysteresis of SLS poly-Si TFT should be improved for a pixel element of high quality AMOLED display.

We have fabricated the new top gate depletion mode n-type alternating magnetic field enhanced rapid thermal annealing (AMFERTA) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which show the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs and excimer laser crystallized (ELC) low temperature polycrystalline silicon (LTPS) TFTs. The fabricated AMFERTA poly-Si TFTs were not degraded under hot-carrier stress, and highly biased vertical field stress. The considerably large threshold voltage shift (ΔVTH) and trap state density reducing were occurred when the gate bias and drain bias were both large enough. The dominant mechanism of instability in the fabricated depletion mode AMFERTA poly-Si TFTs may be due to carrier induced donor-like defects reduction within the channel layer, especially near the drain junction.

We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=−20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

We have fabricated a new magnetic field enhanced solid phase crystallization (FESPC) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs. The mobility (μ) and threshold voltage (VTH) of p-type TFTs of which the channel width and length are 5 μm and 7 μm, respectively are 31.98 cm2/Vs and -6.14 V, at VDS=-0.1 V. In the FESPC TFTs, the characteristics caused by grain boundary are remarkable due to large number of grain boundaries in the channel compared with poly-Si TFTs. The VTH of the TFT which have 5 μm channel length is smaller than that of 18 μm channel length by 1.36 V, which is considerably large value. It is due to the large number of grain boundaries in the channel and the high lateral electric field. The grain boundary potential barrier height is decreased, when the large lateral electric field is applied (which is called DIGBL effect). As a result of increased mobility, the drain current is increased, and VTH can be decreased. The activation energy (Ea) is strongly depended on the drain bias and the number of grain boundaries. is decreased, caused by the large drain bias and/or smaller number of grain boundaries. This decreased Ea can be reduced VTH due to increased the drain current. VTH of p-type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary by increased lateral electrical field.

We have investigated the shift of threshold voltage in the a-Si:H TFT due to the various negative pulse width stress. The drain bias dependent threshold voltage shift in the pulsed stress of a-Si:H TFT for AMOLED backplane is also measured and analyzed. When a positive gate and drain bias is applied to a-Si:H TFT (W/L = 200/4 Ým), VTH of a-Si:H TFT is increased during the stress time due to the defect state creation and charge trapping. VTH of a-Si:H TFT is increased from 1.645V to 2.53V (δVTH=0.885V) after the DC gate bias stress of VGS=15V, VDS=0V for 20,000sec. When the pulsed negative bias stress is applied to the gate electrode of the current driving a-Si:H TFT with the drain bias, VTH shift is considerably reduced due to the hole trapping into the gate insulator during the stress. When a negative pulse width is 16msec (pulse of 60Hz), the VTH is increased form 1.594V to 2.195V (δVTH=0.601V). When a negative pulse width increases from 16msec to 5sec without drain bias (VDS=0V), VTH is increased from 1.615V to 2.055V (δVTH=0.44V). When a drain bias is increased from 0V to 15V, VTH is slightly decreased from 1.58V to 1.529V (δVTH=-0.051V) due to large (-30V) VGD (VG=-15V, VD=15V) bias, while it is increased from 1.66V to 2.078V (δVTH=0.418V) width DC gate bias stress of VGS=15V, VDS=15V for 20,000sec.

The threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.

The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.

The nc-Si films where the troublesome incubation layer was almost eliminated were deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) under various dilution conditions. The nc-Si films were analyzed with cross-sectional high resolution transmission electron microscopy (HR-TEM) images. It was verified that the Si crystalline components formed and grew from the surface of buffer layer. The grain size of 20~50nm was measured. The absence of incubation layer in nc-Si film may be attributed mainly to ICP-CVD which generates remote plasma of high density, the role of hydrogen, and the dilution effect on the growth of crystalline. Our experimental results show that incubation-free nc-Si film deposited by ICP-CVD may be suitable for the active layer of bottom gate nc-Si TFTs as well as top gate nc-Si TFTs.

A top gate pentacene TFT employing vapor deposited polyimide as a gate dielectric was fabricated. Polyimide was co-evaporated from 6FDA and ODA monomers and annealed at 150 °C in vacuum. The degree of imidization was verified by FT-IR. A breakdown voltage of 0.9 MV/cm of polyimide film was measured by MIM structure. A top gate pentacene TFT with W/L=25 has 0.01 cm2/Vs as a mobility, about 103 as an on-off ratio (In/off), −7.5V as a threshold voltage and 9 V per decade as a sub-threshold slope.

We propose a pre-electrical bias aging to reduce threshold voltage (Vth) shift of hydrogenated- amorphous silicon thin-film transistor (a-Si:H TFT) for AMOLED display. The quantity of Vth shift in the sample subjected to a bias-aging is reduced due to the reduction of created dangling bond density, compared with a sample without a bias-aging. When an identical stress duration of 50,000 sec is applied to a-Si:H TFT with or without a pre-electrical bias-aging, the created dangling bond density (ΔNDB) after a pre-electrical bias-aging is decreased from 1.38 × 1011/cm2 to 0.685 × 1011/cm2. Our experimental results indicate that after the pre-electrical bias aging, a newly created dangling bond during an electrical stress is decreased because a weak bond density and hydrogen diffusion may be decreased.

We have proposed low hydrogen concentration (CH) silicon nitride (SiNX) as a dielectric for flexible display application. The fabrication temperature on plastic substrate is limited below Tg (glass transition temperature, typically 130˜180 °C) and it was reported that CH in thin film is strongly depends on fabrication temperature. As the fabrication temperature is decreasing, hydrogen concentration is increasing. SiNX deposited in ultra low temperature (< 150 °C) has high CH which is porous, low density. Our experimental results using SiH4, He, N2 gas mixture shows that in the SiNX CH is less than 15 at.%. Breakdown voltage of proposed SiNX dielectric is 5 MV/cm. In the wet etch rate test using a nitride etching solution, He dilution is more dense than NH3 dilution. This process approach is useful for flexible display application.