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Horizontal carbon nanotube (CNT) interconnects are fabricated using a novel integration scheme yielding record wall densities >1013 shell/cm2, i.e. close to the density required for implementation in advanced integrated circuits. The CNTs are grown vertically from individual via structure and subsequently flipped onto the horizontal wafer surface. Various electrode designs are then used to produce different geometries of metal-to-tube contact such as side contact or end contact. CNT lines - 50 to 100 nm wide and up to 20 µm long - are realized and electrically characterized. The sum of the contact resistances from both ends of the lines is close to 500 Ω for 100 nm diameter lines which leads to a specific contact resistance of 1.6 10-8 Ω.cm2 per tube. With the developed technology, post-annealing of the contact does not improve the resistance values. Both chromium and palladium are used as contact metal. While contact resistance is equivalent with the two metals, the resistance per unit length of the lines does change and is better with palladium. This dependence is explained using a tunnelling model which shows that statistics of individual tube-metal contact is required to properly model the electrical results. Direct experimental evidences showing that only a part of the CNTs in the bundle is electrically connected are also given. Our best line resistivity achieved is 1.6mΩ.cm which is among the best results published for horizontally aligned CNTs and the only one with a realistic geometry for future VLSI interconnects.
This work presents recent advances in the development and the integration of a solid state thin film battery, to work as a high voltage energy source for RF-MEMS powering. Micro-electro-mechanical systems require similarly miniaturized power sources. Up to day, microbatteries are realized with mechanical masks, this method doesn't allow dimensions below several decades of mm2 of active area, and besides the whole process flow is done under controlled atmosphere so as to ensure materials chemical stability (mainly lithiated materials). Within this context, Microelectronics micro-fabrication procedures (photolithography, Reactive Ion Etching…) are used to reach both miniaturisation (100×100 μm2 targeted unit cell active area) and microelectronic IC technological compatibility. The whole process is realized in clean room environment. The thin film battery is composed of three active layers. First the positive electrode layer of crystalline vanadium pentoxide c-V2O5, the next level presents then the solid state electrolyte, a glassy ionic conducting material commonly known as “LiPON”. Finally, a negative electrode top level is realized by the evaporation of metallic lithium. The total stack thickness is of about 10 μm. A final wafer level packaging step is then realized to avoid reactivity with air and moisture. Specific attention will be put on the microfabrication processes developed for the positive electrode and the electrolyte (etching chemistry, resist stripping…). Several electrochemical characterizations (spectroscopic electrochemical impedance, charge-discharge cycling) were performed before and after micro-fabrication process steps so as to evaluate any possible effect on the electrochemical behaviour of the different studied layers.
We discuss applications of statistical-mechanical lattice-gas models to electrochemical adsorption. Our strategy to describe specific systems includes microscopic model formulation, calculation of zero-temperature phase diagrams, numerical simulation of thermody-namic and structural quantities at nonzero temperatures, and estimation of effective, lateral interactions. We report applications to adsorption on single-crystal electrodes, presenting simulated and experimental coverages and voltammetric currents for urea on Pt(100) and the underpotential deposition of Cu on Au(111) in sulfuric acid. We also discuss an extension of the method to study time-dependent phenomena far from equilibrium.
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