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This paper discusses the design steps and experimental characterization of a monolithic microwave integrated circuit (MMIC) power amplifier developed for the next generation of K-band 17.3–20.2 GHz very high throughput satellites. The technology used is a commercially available 100-nm gate length gallium nitride on silicon process. The chip was developed taking into account the demanding constraints of the spacecraft and, in particular, carefully considering the thermal constraints of such technology, in order to keep the junction temperature in all devices below 160°C in the worst-case condition (i.e., maximum environmental temperature of 85°C). The realized MMIC, based on a three-stage architecture, was first characterized on-wafer in pulsed regime and, subsequently, mounted in a test-jig and characterized under continuous wave operating conditions. In 17.3–20.2 GHz operating bandwidth, the built amplifier provides an output power >40 dBm with a power added efficiency close to 30% (peak >40%) and 22 dB of power gain.
This paper describes the development of an L-Band (f0 = 1.575 GHz) high power and efficient solid state power amplifier (SSPA) designed for the European satellite navigation system (i.e. Galileo). The amplifier, developed in the framework of the European Project named SLOGAN, exploits the GH50-10 GaN technology available at United Monolithic Semiconductor foundry. The aim of the project is to offer, using as much as possible European technologies, a valid alternative to replace traveling wave tube amplifiers with more compact and reliable systems. All the SSPA functionalities, i.e. power supply, power conditioning and radio frequency amplification, are integrated in the developed architecture and accommodated in a single box with limited volume and mass. The required output power level is achieved by parallelizing several GaN die power bars of 12 and/or 25.6 mm. In continuous wave operating mode, the overall SSPA delivers an output power higher than 250 W at less than 2 dB of gain compression in the whole E1-band. Moreover, the registered gain and efficiency are higher than 67 dB and 54%, respectively.
A combined class-AB and a Doherty power amplifier conceived for microwave backhaul in the 7 GHz frequency band are here presented and compared. They are fabricated in the same GaN monolithic process and have identical total active device periphery. For the given application, the linearity-efficiency trade-off for the two architectures is discussed. The two modules have been thoroughly characterized in linear and non-linear continuous wave conditions. Then, to evaluate linearity under the actual operative conditions, a system level characterization has been carried out, applying a modulated input signal and comparing the spectral responses of the two amplifiers with and without digital predistortion. A saturated output power of 40 dBm has been achieved by both circuits. At 6 dB of output back-off, the Doherty amplifier shows an efficiency of 33%, 10 points higher than that of the class-AB module. On the other hand, system level measurements show that, adopting the same predistorter complexity to comply with the reference standard emission masks, the Doherty amplifier needs at least 1 dB of extra back-off. This negatively affects its efficiency, therefore reducing the advantages it can claim with respect to the class-AB amplifier in continuous wave condition.
The aim of the present paper is to highlight the possible benefits coming from the use of the GaN high electron-mobility transistor (HEMT) technology in the Doherty power amplifier (DPA) architecture. In particular, the attention is focused on the capabilities and the relevant drawbacks of a GaN HEMT technology when designing DPAs. A deep discussion of the DPA's design guidelines is also presented through the realization of three prototypes implementing different design solutions and working at 2.14 GHz. The first example is a tuned load DPA (TL-DPA), which show an average drain efficiency of 40.7% with 3 W of saturated output power in the obtained 6 dB of output back-off. The second DPA was designed implementing a class F harmonic termination for the main device, which allows an improvement of roughly 15% in output power and efficiency behavior with respect to the TL-DPA. The last DPA was realized implementing a single output matching network for both main and auxiliary devices, which allows a relevant reduction in the size of the resulting DPA, without downgrading the overall performances.
This paper reports an investigation and a proposed solution to design Class E power amplifiers above the theoretical maximum frequency allowed by the adopted active device. Starting from the traditional time domain analysis, a numerical algorithm has been developed and presented in order to extend Class E feasibility through the optimization of the output voltage waveform. A hybrid Class E amplifier in laterally diffused metal oxide semiconductor (LDMOS) technology has been designed and measured. The final amplifier shows an output power of more than 10 W with an associated efficiency of 49% (power added efficiency (PAE) = 45%) over a 100-MHz bandwidth around 2.14 GHz.
In this paper, the main nonidealities appearing in polar transmitters will be addressed, together with several implementation considerations. Special attention will be paid to the role of AM modulation nonlinearity and parasitic AM-to-PM conversion, once architecture mechanisms such as time-delay mismatch between branches or limited bandwidth in the amplitude path are controlled. The device limiting factors for a highly efficient switched mode operation and a linear amplitude modulation will be identified. Some circuit design and implementation guidelines for the RF modulating stage and the envelope amplifier will be discussed, to finish with system-level analysis considerations under two-tone and real communication signal excitations.
This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.
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