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Horizontal carbon nanotube (CNT) interconnects are fabricated using a novel integration scheme yielding record wall densities >1013 shell/cm2, i.e. close to the density required for implementation in advanced integrated circuits. The CNTs are grown vertically from individual via structure and subsequently flipped onto the horizontal wafer surface. Various electrode designs are then used to produce different geometries of metal-to-tube contact such as side contact or end contact. CNT lines - 50 to 100 nm wide and up to 20 µm long - are realized and electrically characterized. The sum of the contact resistances from both ends of the lines is close to 500 Ω for 100 nm diameter lines which leads to a specific contact resistance of 1.6 10-8 Ω.cm2 per tube. With the developed technology, post-annealing of the contact does not improve the resistance values. Both chromium and palladium are used as contact metal. While contact resistance is equivalent with the two metals, the resistance per unit length of the lines does change and is better with palladium. This dependence is explained using a tunnelling model which shows that statistics of individual tube-metal contact is required to properly model the electrical results. Direct experimental evidences showing that only a part of the CNTs in the bundle is electrically connected are also given. Our best line resistivity achieved is 1.6mΩ.cm which is among the best results published for horizontally aligned CNTs and the only one with a realistic geometry for future VLSI interconnects.
In future technology nodes, 22nm and below, carbon nanotubes (CNTs) may provide a viable alternative to Cu as an interconnect material. CNTs exhibit a current carrying capacity (up to 109 A/cm2), whilst also providing a significantly higher thermal conductivity (SWCNT ~ 5000 WmK) over Copper (106 A/cm2 and ~400WmK). However, exploiting such properties of CNTs in small vias is a challenging endeavor. In reality, to outperform Cu in terms of a reduction in via resistance alone, densities in the order of 1013 CNTs/cm2 are required. At present, conventional thermal CVD of carbon nanotubes is carried out at temperatures far in excess of CMOS temperature limits (400 C). Furthermore, high density CNT bundles are most commonly grown on insulating supports such as Al2O3 and SiO2 as they can effectively stabilize metallic nanoparticles at elevated temperatures but this limits their application in electronic devices. To circumvent these obstacles we employ a remote microwave plasma to grow high density CNTs at a temperature of 400 C on conductive underlayers such as TiN. We identify some critical factors important for high-quality CNTs at low temperatures such as control over the catalyst to underlayer interaction and plasma growth environment while presenting a fully CMOS compatible carbon nanotube synthesis approach
Because of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.
The use of carbon nanotubes (CNT) as interconnects in future integrated circuits (IC) is being considered as a replacement for copper. As this research needs also innovative metrology solutions, we have developed a combined approach for the plane-view analysis of CNT integrated in contact holes where transmission electron microscopy (TEM) enables the quantitative measurement of density and structure of the CNT and where scanning spreading resistance microscopy (SSRM) is used to electrically map the distribution of the CNT. This paper explains the used methodologies in detail and presents results from 300 nm diameter contact holes filled with CNT of 8-12 nm in diameter and a density of about 2 x 1011 cm-2.
The integration of high-density CNT bundles as via interconnects in a CNT/Cu-hybrid BEOL stack is evaluated. CNT via-conduits may greatly improve heat dissipation and as such lower interconnect resistance and improve electromigration resistance. Each carbon shell of the nanotube contributes to electrical and thermal conduction and densities as high as 5×1013 shells per cm2 are estimated necessary. CNT growth processes on BEOL compatible metals are presented with tube densities up to 1012cm−2 and shell densities approaching 1013 cm−2 on blanket substrates. Selective growth of CNT bundles with carbon shell densities around 1012cm−2 is demonstrated with high yield. Ohmic behavior of TiN/CNT/Ti contacts is shown with a CNT via resistivity of 1.2 mΩ cm.
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