We have investigated the reliability of the inverted-staggered etch stopper structure oxide-based TFTs under negative gate bias stress combined with 400 nm wavelength light illumination and the relationship between the carrier concentration at the channel and the extent of Vth shift. It was found that the photo-induced holes cause the severe Vth degradation at the beginning of stress and the hole trapping rate of a single hole is not altered with the increase of the hole concentration. In oxide-based TFTs, the hole concentration at the channel is the determinant factor of the reliability.

We have investigated the stability of short channel (1.5μm) p-Type polycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate under AC bias stress. The variation of threshold voltage in short channel poly-Si TFT was considerably higher than that of long channel poly-Si TFT. Threshold voltage of the short channel TFT was considerably moved to the positive direction during AC bias stress, whereas the threshold voltage of a long channel was rarely moved. The variation of threshold voltage in the short channel p-type TFT under AC bias stess was more compared to that under DC bias stress. The threshold voltage of short channel (L=1.5μm) poly-Si TFT was increased about -7.44V from -0.305V to -7.745V when VGS = 5 (base value) ~ -15V (peak value), VDS = -15V was applied for 3,000 seconds. This positive shift of threshold voltage and significantly degraded s-swing value in the short channel TFT under dynamic stress (AC) may be due to the increase of the stress-induced trap state density at gate insulator / channel interface region.

We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=-20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. . We also applied same off state bias annealing at SPC-Si TFT with 20,000 lx light illumination in order to verify the reduction of leakage current of SPC-Si TFT under light illumination. The leakage current of SPC-Si TFT was reduced successfully even under light illumination during off-state bias annealing. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

We have propsed MgO/AZO bi-layer transparent conducting oxide (TCO) for thin film solar cells. From XRD analysis, it was observed that the full width at half maximum of AZO decreased when it was grown on MgO precursor. The Hall mobility of MgO/AZO bi-layer was 17.5cm2/Vs, whereas that of AZO was 20.8cm2/Vs. These indicated that the crystallinity of AZO decreased by employing MgO precursor. However, the haze (=total diffusive transmittance/total transmittance) characteristics of highly crystalline AZO was significantly improved by MgO precursor. The average haze in the visible region increased from 14.3 to 48.2%, and that in the NIR region increased from 6.3 to 18.9%. The reflectance of microcrystalline silicon solar cell was decreased and external quantum efficiency was significantly improved by applying MgO/AZO bi-layer TCO. The efficiency of microcrystalline silicon solar cell with MgO/AZO bi-layer front TCO was 6.66%, whereas the efficiency of one with AZO single TCO was 5.19%.

We successfully fabricated a-IGZO TFTs employing a Ti/Cu source/drain (S/D) and SiNx passivation in order to reduce the line-resistance, as compared to most oxide TFTs that use Mo (or TCO) and SiO2 for their S/D and passivation, respectively. Although passivated with SiNx, the TFT exhibits good transfer characteristics without a negative shift. However, the TFT employing a Mo S/D exhibited conductor-like characteristics when passivated with SiNx. Our investigation suggests that the IGZO oxygen vacancies found in the Ti/Cu S/D are controlled, resulting in low concentrations, and so prevent the SiNx-passivated TFT from having a negative shift.

We have investigated the effects of hydrogen plasma treatment on the hysteresis phenomenon and electrical properties of solid phase crystallized silicon thin film transistors (SPC-Si TFTs) employing alternating magnetic field crystallization (AMFC). We employed H2 plasma treatment on the SPC-Si active layer before SiO2 gate insulator deposition. By increasng the power and time duration of H2 plasma treatment, it was observed that hysteresis phenomenon of SPC-Si TFT was suppressed and electrical properties such as threshold voltage, field effect mobility was improved considerably. This is due to role of hydrogen atom by passivating the defects and grain boundary trap states in SPC-Si film. However, relatively high power and long hydrogen plasma treatment (100W, 5 minutes) could degrade the electrical characteristics of the device. SPC-Si TFT for 100W power of PECVD and 3 minutes with the H2 plasma treatment exhibit the significant improvement of electrical characterics (VTH = - 3.85V, μFE = 21.16cm2/Vs), and a smaller hysteresis phenomenon (∆VTH = -0.30V) which is suitable for high quality AMOLED Display.

We fabricated highly transparent and high haze ZnO:Al film for front TCO of amorphous and microcrystalline silicon solar cells. We have sputtered ZnO:Al film of 1.3 μm on the thin seed layer of about 60nm which was previously sputtered on the glass substrate by using 4% dilution of oxygen to argon gas. The ZnO:Al film grown on the seed layer had much higher crystalline phase than one without any seed layer. Our bi-layer ZnO:Al film showed low resistivity of 2.66×10-4 Ω•cm and sheet resistance of 2.08 Ω/⇐ while conventional ZnO:Al film showed resistivity of 3.24×10-4 Ω•cm and sheet resistance of 2.46 Ω/⇐. After surface texturing by 0.5% HCl wet-chemical etching, the transmittance of ZnO:Al film was increased from 83.7% to 88.1% at wavelength of 550nm through the seed layer. Also the transmittance at 800nm was increased from 82.3% to 88.9%. Especially, haze values of the ZnO:Al film were drastically increased from 58.7% to 90.6% at wavelength of 550nm by employing the seed layer. Also haze values at 800nm were increased from 22.1% to 68.1%. It is expected that the seed layer method to improve the quality of ZnO:Al film will contribute to an increase of solar cell efficiency due to the high capability of light trapping and low electrical resistivity.

We have investigated the change of the Schottky contact surface and the interface between Schottky metals and AlGaN/GaN heterostructure after the annealing process for 35 min at 300 °C. The secondary ion mass spectroscopy (SIMS) and the scanning electron microscopy (SEM) show that the Schottky metals and AlGaN/GaN heterostructure interacted actively during the annealing process. The atoms in Schottky contact and AlGaN/GaN heterostructure diffused interactively and the surface roughness of Schottky contact was increased. After the annealing process for fabricated AlGaN/GaN High-Electron-Mobility Transistor (HEMT), the threshold voltage was shifted by +0.2 V and the leakage current was decreased by 40 %.

We fabricated nc-Si TFTs in order to investigate the effect of the active-layer thickness on the characteristic of the nc-Si TFT. Bottom gate nc-Si TFTs were fabricated at 350°C using ICP-CVD. The thicknesses of the nc-Si layer were remained to 700, 1200 and 1700 Å. As the active-layer thickness increases, the mobility and the on-current level were not altered. However, the off-current level increased considerably and on/off ratio decreased. It may be attributed to highly doped characteristic of thick nc-Si film. As the nc-Si film thicker, the conductivity increases considerably and the Fermi level approaches to the conduction band minimum, which indicates the increases of doping level. The oxygen concentration shows high level of unintentional doping. Also, columnar growth of nc-Si film makes that the crystallinity of top region is much higher than that of bottom region. So, the conductivity of thick nc-Si film becomes high compared to that of thin nc-Si film. The structure of the nc-Si TFT with thick nc-Si film can be similar to the serial connection of N+, N- and N+ resistance, so that it suffers difficulty to suppress the off current and to secure high on/off ratio. Therefore, the off current can be suppressed by thinning of the high conducting active nc-Si layer and nc-Si TFT with channel thickness of 700 Å shows good on/off characteristic. It is deduced that bottom gate nc-Si TFT is necessary to have intrinsic channel layer as well as thin channel layer to reduce the leakage current.

Considerable amount of works have been reported to achieve a high breakdown voltage of AlGaN/GaN heterostructure devices by employing additional process such as SiO2 passivation1,2, floating metal rings and Ni/Au Oxidation3. However, it should be point out that treatment of passivation layer of AlGaN/GaN heterostructure devices has been reported scarcely. As+ ion implantation on SiO2 passivation layer may be a simple and effective to reduce electric field strength to increase breakdown voltages. The cross-sectional view of the proposed AlGaN/GaN Schottky barrier diode is shown in Fig. 1. We fabricated conventional AlGaN/GaN Schottky barrier diode and passivated the device with SiO2 layer of 350 nm thick. Finally As+ ions were implanted on the SiO2 passivation layer. We measured the surface potential of the test samples with electric force microscopy (EFM) in order to verify that implanted As+ ions remained as positively charged ions in SiO2 layer after ion implantation. After ion implantation, 2 dimensional electron gas (2DEG) concentration was increased slightly from 8.28E12 /cm2 to 8.38E12 /cm2 so that the forward current was also increased slightly. Table shows the breakdown voltages of the SBDs before and after As+ ion implantation. After As+ 80 keV 1 × 1E14 atoms/cm2 implantation, the breakdown voltage increased considerably from 604 V to 1204 V due to the edge termination by implanted As+ ions. The reverse leakage current decreased from 80.3 uA/mm to 21.2 nA/mm due to the relaxation of electric field concentration by As+ ion implantation. We verified the electric field relaxation through 2D simulation. After As+ ion implantation, the depletion region curvature under the reverse biased condition became moderate so that the maximum electric field strength was decreased. As+ ion implantation method may be a simple and effective edge termination method for improving the breakdown voltage as well as the leakage current of the proposed AlGaN/GaN SBDs. Proposed AlGaN/GaN SBDs showed high breakdown voltage of 1204 V and low leakage current of 21.2 nA/mm without any considerable decrease of forward characteristics while that of conventional device was 604 V and 80.3 uA/mm, respectively.

We have investigated temperature dependence on the hysteresis phenomenon of SLS poly-Si TFT on a glass substrate, extremely at low temperature (213K). The p-type sequential lataral solidification (SLS) polycrystalline Silicon (poly-Si) TFT was fabricated on glass substrate. As the temperature was reduced, it was observed that hysteresis phenomenon was increased, whereas the hysteresis was suppressed at high temperature. This could be explained by a difference of initially electron and hole trapped charges into gate insulator is much larger in low temperature than in high temperature. And we have verified that drain current was changed with a different previous gate starting voltage even at same bias condition by experimental results due to the hysteresis phenomenon of SLS poly-Si TFT. Hysteresis of SLS poly-Si TFT should be improved for a pixel element of high quality AMOLED display.

We have fabricated the new top gate depletion mode n-type alternating magnetic field enhanced rapid thermal annealing (AMFERTA) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which show the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs and excimer laser crystallized (ELC) low temperature polycrystalline silicon (LTPS) TFTs. The fabricated AMFERTA poly-Si TFTs were not degraded under hot-carrier stress, and highly biased vertical field stress. The considerably large threshold voltage shift (ΔVTH) and trap state density reducing were occurred when the gate bias and drain bias were both large enough. The dominant mechanism of instability in the fabricated depletion mode AMFERTA poly-Si TFTs may be due to carrier induced donor-like defects reduction within the channel layer, especially near the drain junction.

We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=−20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

Silicon dioxide (SiO2) films were deposited on crystalline silicon substrate by inductively coupled plasma chemical vapor deposition (ICP-CVD). In this paper, various process parameter-gas flow rate, ICP RF power, Process pressure were discussed for the investigation of refractive index. And some properties of the SiO2 film are investigated. Since there was no external substrate heating during the deposition, the SiO2 film showed poor electrical characteristics, such as shifted flat-band voltage and high effective charge density. We have proposed He plasma pre-treatment in order to reduce the interface fixed charge and some post-treatment. Our experimental results shows that He plasma pre-treatment supply thermal energy for decomposition of reactant gas and to remove effective charges. Hydrogen post-treatment also enhances electrical characteristics. We measured the effect of the plasma treatment using FT-IR spectrum and C-V characteristics.

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) of which active layer thickness was 100nm were fabricated using inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150°C. The fabricated nc-Si TFT exhibits rather high field effect mobility exceeding 22cm2/Vs and excellent sub-threshold slope of 0.45V/dec. The nc-Si film deposited 150°C as an active layer of the TFT shows high crystallinity more than 70% and very thin incubation layer less than 20nm. ICP-CVD provides high density plasma with reduced ion bombardment during the deposition on nc-Si and He dilution can enhance the decomposition of SiH4 into Si, SiHX radicals and atomic H, so that high quality nc-Si film can be fabricated. The gate insulator SiO2 film deposited by ICP-CVD at 150°C shows good electrical characteristics such as flat band voltage of -1.8V and breakdown voltage of 6.2MV/cm.

We have fabricated a new magnetic field enhanced solid phase crystallization (FESPC) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs. The mobility (μ) and threshold voltage (VTH) of p-type TFTs of which the channel width and length are 5 μm and 7 μm, respectively are 31.98 cm2/Vs and -6.14 V, at VDS=-0.1 V. In the FESPC TFTs, the characteristics caused by grain boundary are remarkable due to large number of grain boundaries in the channel compared with poly-Si TFTs. The VTH of the TFT which have 5 μm channel length is smaller than that of 18 μm channel length by 1.36 V, which is considerably large value. It is due to the large number of grain boundaries in the channel and the high lateral electric field. The grain boundary potential barrier height is decreased, when the large lateral electric field is applied (which is called DIGBL effect). As a result of increased mobility, the drain current is increased, and VTH can be decreased. The activation energy (Ea) is strongly depended on the drain bias and the number of grain boundaries. is decreased, caused by the large drain bias and/or smaller number of grain boundaries. This decreased Ea can be reduced VTH due to increased the drain current. VTH of p-type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary by increased lateral electrical field.

We have investigated the shift of threshold voltage in the a-Si:H TFT due to the various negative pulse width stress. The drain bias dependent threshold voltage shift in the pulsed stress of a-Si:H TFT for AMOLED backplane is also measured and analyzed. When a positive gate and drain bias is applied to a-Si:H TFT (W/L = 200/4 Ým), VTH of a-Si:H TFT is increased during the stress time due to the defect state creation and charge trapping. VTH of a-Si:H TFT is increased from 1.645V to 2.53V (δVTH=0.885V) after the DC gate bias stress of VGS=15V, VDS=0V for 20,000sec. When the pulsed negative bias stress is applied to the gate electrode of the current driving a-Si:H TFT with the drain bias, VTH shift is considerably reduced due to the hole trapping into the gate insulator during the stress. When a negative pulse width is 16msec (pulse of 60Hz), the VTH is increased form 1.594V to 2.195V (δVTH=0.601V). When a negative pulse width increases from 16msec to 5sec without drain bias (VDS=0V), VTH is increased from 1.615V to 2.055V (δVTH=0.44V). When a drain bias is increased from 0V to 15V, VTH is slightly decreased from 1.58V to 1.529V (δVTH=-0.051V) due to large (-30V) VGD (VG=-15V, VD=15V) bias, while it is increased from 1.66V to 2.078V (δVTH=0.418V) width DC gate bias stress of VGS=15V, VDS=15V for 20,000sec.

The threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.

The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.

An asymmetric dual gate poly-Si thin film transistors (TFTs), which is consist a long-gate TFT and a short-gate TFT, were fabricated in order to suppress the kink current and increase the reliability. The long-gate TFT operates in a linear regime and limits the total current flow by its current operation region. The asymmetric dual-gate does not exhibit from the kink current in a high drain bias due to the distribution of lateral electric field. The asymmetric dual-gate structure improves kink-free characteristics compared with conventional single and dual-gate TFTs. The hot-carrier stress reliability is successfully improved due to kink current suppression.

The nc-Si films where the troublesome incubation layer was almost eliminated were deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) under various dilution conditions. The nc-Si films were analyzed with cross-sectional high resolution transmission electron microscopy (HR-TEM) images. It was verified that the Si crystalline components formed and grew from the surface of buffer layer. The grain size of 20~50nm was measured. The absence of incubation layer in nc-Si film may be attributed mainly to ICP-CVD which generates remote plasma of high density, the role of hydrogen, and the dilution effect on the growth of crystalline. Our experimental results show that incubation-free nc-Si film deposited by ICP-CVD may be suitable for the active layer of bottom gate nc-Si TFTs as well as top gate nc-Si TFTs.