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High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials.
Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface.
Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs.
Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.
Future CMOS technologies will require the use of substrate material with a very high mobility. Therefore, the combination of Ge pMOS with GaAs nMOS devices is investigated for its possible use in advanced CMOS applications. In this work, the physical, chemical and electrical properties of a-GeO2 interfacial passivation layer (IPL) for n-Ge(001) and p-GaAs(001) have been investigated, using Molecular Beam Epitaxy (MBE) technique. The efficient electrical passivation of Ge/GeO2 will be demonstrated, and in the case of GaAs, the use of a thin a-GeO2 interlayer reduces the defects at the interface.
Catalytic-FGA, a combination of the standard forming gas anneal with a catalytic metal gate, has been applied to study the hydrogen passivation of III-V/Ge MOS systems. Pd (or Pt) metal gate catalytically dissociates molecular hydrogen into atomic hydrogen atoms, which then diffuse through the dielectric layer and neutralize certain semiconductor/dielectric interfacial defects. MOS systems with various interfacial qualities, including lattice-matched (n/p) In0.53Ga0.47As/10nm ALD-Al2O3 (or ZrO2)/Pd capacitors, an undoped Ge/˜1nm GeO2/4nm ALD-Al2O3/Pt capacitor, and an nGe/8nm ALD-Al2O3/Pt capacitor are fabricated to evaluate the effectiveness of C-FGA.
Ultrathin lanthanide (Nd, Pr, Eu, Sm) oxide films with functional dielectric properties down to 3.3 nm thickness were deposited by aqueous chemical solution deposition (CSD) onto hydrophilic SiO2/Si substrates. Precursor solutions were prepared from the oxides via an intermediate, solid Ln(III)citrate. A film heat treatment scheme was derived from thermogravimetric analysis of the precursor gels, showing complete decomposition by 600 °C. Crystalline phase formation in the films depended on the lanthanide, annealing temperature, and citric acid content in the precursor. Through variation of the precursor concentration and number of deposited layers, thickness series of uniform films were obtained down to ∼3 nm. The film uniformity was demonstrated both by atomic force microscopy and cross-section transmission electron microscopy. The lanthanide oxide films possessed good dielectric properties. It was concluded that aqueous CSD allows deposition of uniform ultrathin films and may be useful for the evaluation of new high-k candidate materials.
The use of Au nanoparticles as catalysts for growth of Si nanowires poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts can be broadened when the need for catalytic precursor dissociation is eliminated. However, the requirements for selective deposition in a gas phase transport -limited regime become stringent. When competing deposition of amorphous Si can bury the particles faster than the incubation time for VLS growth, no nanowire growth will be initiated. We show that the use of a catalyst such as In, already in a liquid form at the growth temperature, is effective. Therefore, the choice of VLS catalysts among the low melting point metals from the III, IV and V groups is suggested.
Detailed investigations of strain generation and relaxation in Si films grown on thin Si0.78Ge0.22 virtual substrates using Raman spectroscopy are presented. Good virtual substrate relaxation (>90%) is achieved by incorporating C during the initial growth stage. The robustness of the strained layers to relaxation is studied following high temperature rapid thermal annealing typical of CMOS processing (800-1050 °C). The impact of strained layer thickness on thermal stability is also investigated. Strain in layers below the critical thickness did not relax following any thermal treatments. However for layers above the critical thickness the annealing temperature at which the onset of strain relaxation occurred appeared to decrease with increasing layer thickness. Strain in Si layers grown on thin and thick virtual substrates having identical Ge composition and epilayer thickness has been compared. Relaxation through the introduction of defects has been assessed through preferential defect etching in order to verify the trends observed. Raman signals have been analysed by calibrated deconvolution and curve-fitting of the spectra peaks. Raman spectroscopy has also been used to study epitaxial layer thickness and the impact of Ge out-diffusion during processing. Improved device performance and reduced self-heating effects are demonstrated in thin virtual substrate devices when fabricated using strained layers below the critical thickness. The results suggest that thin virtual substrates offer great promise for enhancing the performance of a wide range of strained Si devices.
In the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.
This paper investigates the possibility of reducing the deposition temperature of polycrystalline silicon germanium to a level compatible with complementary metal-oxide semiconductor (CMOS) post processing. To achieve this goal, the exact wafer temperature during deposition was experimentally determined and it was found to be 30 °C lower than the reactor setting temperature. The deposition temperature was reduced from 625 to 500 °C. The impact of varying the deposition pressure from 10 to 760 torr and the germanium content from 15% to 100% was investigated. X-ray diffraction spectroscopy and transmission electron microscopy showed that the SixGe1−x films deposited at an actual wafer temperature of 520 °C are polycrystalline for germanium contents as low as 15%. Also, it was shown that the deposition conditions can be adjusted to yield a low tensile stress at an actual wafer temperature of 520 °C, which is suitable for integrating surface micromachined micro-electromechanical systems on top of standard CMOS wafers with Al interconnects.
Si based nanostructures such as Ge or Si1-xGex dots embedded in Si receive a lot of attention. This interest is driven by the reduction of device sizes as well as by their possible use in opto-electronic applications, as a possible solution to improve the radiative light emission. In this paper we give a detailed overview of the growth kinetics as observed for Ge growth in a standard production oriented chemical vapor deposition system. The island morphology and density are controlled by varying the growth conditions or by applying a thermal anneal after the island growth. Island densities up to 2.3x1010 cm−2 have been obtained for depositions at 650°C. With increasing deposition time, the usual change-over from monomodal to bimodal island distribution is pointed out and this change-over depends on the critical island diameter, which decreases with decreasing growth temperature. Applying a thermal budget after the island growth initiates Ge surface diffusion and Si diffusion from the substrate through the islands. This results in an enhancement of the island diameter and height, and also in a reduction of island density. Furthermore, depending on the island distribution after Ge deposition, a transition from pyramid to dome or visa versa is observed after the in-situ anneal. Optical device structures require a Si cap layer. However, Si capping at 700°C, leads to a nearly total dissolution of small islands and a truncation of bigger dome-shaped islands. This can be prevented by reducing the deposition temperature and by changing the Si gas source. Clear island luminescence, is observed up to 200K and lies in the spectral range of 1.35-1.50μm, which is interesting from the point of view of applications. In particular, this shows the potential of this material system for opto-electronic device applications. In spite of the fact that the observed PL intensity is comparable to the best reported values, we could further enhance it by a thermal treatment in a H2 plasma.
MicroElectroMechanical Systems (MEMS) are used in a wide variety of applications such as accelerometers , gyroscopes , infrared detectors ,…etc. For high volume applications, fabrication costs can be possibly reduced by monolithic integration of MEMS with the driving electronics. The easiest approach for monolithic integration is post processing MEMS on top of the driving electronics, as this does not introduce any change into standard fabrication processes used for realizing the driving electronics. On the other hand, post processing imposes an upper limit on the fabrication temperature of MEMS in order to avoid any damage or degradation in the performance of the driving electronics. Polycrystalline silicon (Poly Si) has been widely used for MEMS applications , but the main disadvantage of this material is that it requires a high processing temperature (higher than 800°C ) to achieve the desired physical properties. In particular, a low tensile stress is needed for MEMS. Polycrystalline silicon germanium (Poly SiGe) seems to be an attractive alternative to poly Si as it has similar properties, while the presence of germanium reduces its melting point. Hence, the desired physical properties are expected to be realized at lower temperature. Depending on the germanium concentration and the deposition pressure, the transition temperature from amorphous to polycrystalline can be reduced to 450°C , or even lower, compared to 580°C for LPCVD poly Si. Also, the residual mechanical stress in poly SiGe is lower than that in poly Si .
By Pulsed Gas CVD-growth, heteroepitaxial growth of pure Ge-layers from pure GeH4 has been accomplished at 650 °C on Si-substrates without intermediate Si1−xGex-bufferlayers. The material has been studied by means of RBS, SEM, ECP, XRD and cross-sectional, highresolution and plan-view TEM. The thickness of the Ge-layers varied between 2 and 24 monolayers. From 5 monolayers on, some part of the Ge appears to be fully relaxed. Uptill 12 monolayers, the growth is fully 2-dimensional and results in specular, flat surfaces; for thicker layers islanding starts (Stranski-Krastanow growth). The material is completely defect-free. According to XRD-measurements, the perpendicular strained Ge-cell dimension is 5.748 Å, which is very reproducible for all layer-thicknesses. Nevertheless, from linear elastic theory considerations, it should be 5.83 Å. The Ge-layers so formed appear to be suitable for use in short-period (SinGem)p-superlattices.
For low-temperature epi-growth in UHV-CVD-systems, the pre-epi, ex-situ cleaning of Si-wafers is known to be very critical. Various ways of etching the chemical oxide-layer after RCA-cleaning have been analysed by SIMS-measurements of the interfacial C, 0 and Bcontamination. Layer growth was performed at 650 C under a flow of 20 sccm of silane at 0.26 Pa. The best results (C and 0 below 2 % of a monolayer, and no detectable amounts of B) were obtained with “dry” etch-procedures, i.e. in which no water-rinse was applied after a normal 2 % HF-dip, or where 1F-vapour was used instead. Growth of Si1-xGex-layers with x < 0.1 succeeds quite well on such prepared substrates; for x between 0.1 and 0.25, we have found the use of a thin, pure Si-buffer layer (150 Å) to be indispensable. For x > 0.25, the growing layer can become quite rough, although this varies in time.
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