An organic/inorganic hybrid-type nonvolatile memory TFT was proposed as a core device for the future flexible electronics. The structural feature of this memory TFT was that a ferroelectric copolymer and an oxide semiconductor layers were employed as a gate insulator and an active channel, respectively. The memory TFT with the structure of Au/poly(vinylidene fluoride-trifluoroethylene)/Al2O3/ZnO/Ti/Au/Ti/poly(ethylene naphthalate) could be successfully fabricated at the process temperature of below 150°C. It was confirmed that the TFT well operated as a memory device even under the bending situations.

The SrTa2O6 (STO) thin films were prepared by plasma enhanced atomic layer deposition (PEALD) with alternating supply of reactant sources, Sr[Ta(C2H5O)5(C4H10NO)]2 {Strontium bis-[tantalum penta-ethoxide dimethyllaminoethoxide]; Sr(Ta(OEt)5▪dmae)2} and O2plasma. It was observed that the uniform and conformal STO thin films were successfully deposited using PEALD and the film thickness per cycle was saturated at about 0.8 nm at 300°C. Electrical properties of SrTa2O6 (STO) thin films prepared on Pt/SiO2/Si substrates with annealing temperatures have been investigated. While the grain size and dielectric constant of STO films increased with increasing annealing temperature, the leakage current characteristics of STO films slightly deteriorated. The leakage current density of a 40nm-STO film was about 5×10−8A/cm2 at 3V.

We have grown well-aligned carbon nanotube arrays by thermal chemical vapor deposition at 800°C on Fe nanoparticles deposited by a pulsed laser on a porous Si substrate. Porous Si substrates were prepared by the electrochemical etching of p-Si(100) wafers with resistivities of 3 to 6 ωcm. These well-aligned carbon nanotube field emitter arrays are suitable for electron emission applications such as cold-cathode flat panel displays and vacuum microelectronic devices like microwave power amplifier tubes. Field emission characterization has been performed on the CNT-cathode diode device at room temperature and in a vacuum chamber below 10−6 Torr. The anode is maintained at a distance of 60[.proportional]m away from the carbon nanotube cathode arrays through an insulating spacer of polyvinyl film. The measured field emitting area is 4.0×10−5cm2. Our carbon nanotube field emitter arrays emit 1mA/cm2at the electric field, 2V/[.proportional]m. And they emit a large current density as high as 80mA/cm2 at 3V/[.proportional]m. The open tip structure of our carbon nanotubes and their good adhesion through Fe nanoparticles to the Si substrate are part of the reason why we can attain a large field emission current density within a low field. The field emitter arrays in our diode device are vertically well-aligned carbon nanotubes on the Si-wafer substrate.

Si/Si0.8Ge0.2/Si(001) structures were grown at various growth temperatures (250 ∼ 760 °C) using molecular beam epitaxy, and the variation of strain and microstructure of the film was investigated using double crystal X-ray diffractometry and transmission electron microscopy. SiGe films with good single crystallinity were obtained at the growth temperatures of 440 ∼ 600 °C. For the samples grown below 350 °C, an amorphous SiGe film was developed over the SiGe single crystalline layer with a jagged amorphous/crystalline (a/c) interface, and many defects such as stacking faults and microtwins were formed below the a/c interface. Dislocations were developed through out the films for the samples grown above 680 °C. In addition, for the samples grown below 680 °C, the amount of in-plane strain of the SiGe film was found to be about − 8×l0−3 without strain relaxation. However, the SiGe films grown at 760 °C have small in-plain strain of − 4×l0−3 and large strain relaxation of 50%.

The effect of growth interruption (GI) on the quality of interface between InGaAs quantum well (QW) and InP layer has been studied using transmission electron microscopy (TEM). The In1-xGaxAs (x=0.39) QW grown without GI has sharp and coherent interfaces. However, cellular structure instead of InGaAs QW was observed in the sample grown with 120 sec AsH3 purge during the first GI (before the growth of InGaAs QW). According to the composition analysis using energy dispersive X-ray (EDX), inside of cell is InP and boundary of cell is considered to be a mixture of In1-xGaxAs1-yPy and InAs1-xPx phases. Similar structure was observed in the sample grown with 30 sec AsH3 purge after 30 sec PH3 purge during the first GI. Our results indicate that long time AsH3 purge during the first GI is detrimental to the formation of InGaAs QW. For the sample grown with AsH3 purge less than 40 sec during the second GI (after the growth of InGaAs QW), InGaAs QW is formed with sharp and coherent interfaces. However, if the surface of InGaAs QW is exposed to AsH3 gas for long time (~ 120 sec), dislocations are generated at the interface bewteen InGaAs QW and InP cap layer.

For the GaAs buffer layer deposited on Si substrate at 80°C and annealed at 300°C for 10 min, the size of most GaAs islands was observed as ∼ 10 nm but large islands (∼ 40 nm) were also seen. According to the calculation of spacing of moire fringes, large GaAs islands are considered to be rotated about 4 ° with respect to the Si substrate normal. However, for the main GaAs film overgrown on the GaAs buffer layer at 580 °C, moire fringes with the spacing of 5 nm (GaAs film without rotation) completely covered the surface of Si substrate. Misfit dislocations and stacking faults were already formed at the growth stage of buffer layer. Stacking faults and misfit dislocations consisting of Lomer and 60 ° dislocations were observed in GaAs films grown at 580 °C. However, after rapid thermal annealing at 900 °C for 10 sec, only Lomer dislocations with 1/2[110] and 1/2[-110] Burgers vectors were observed.