In this work, the electrical properties of heavily doped poly-SiGe deposited at temperatures compatible with MEMS integration on top of standard CMOS are reported. The properties studied are resistivity, temperature coefficient of resistance, noise, piezoresistivity, Hall mobility and effective carrier concentration. The obtained results prove the potential of using poly-SiGe as a sensing layer for MEMS-above-CMOS applications.

This work reports on the performance of different Hafmiun aluminate (HfAlOx)-based interpoly dielectrics (IPD) for future sub-45nm nonvolatile memory (NVM) technologies. The impact of the thermal budget during the fabrication process is studied. The good retention and large operating window shown by this material, can be compromised by a high temperature activation anneal (AA) after the gate deposition. The AA step may induce phase segregation of the HfAlOx and outdiffusion of the Hf (Al) towards the floating gate/IPD and IPD/gate interfaces and subsequent formation of Hf (Al) silicates. These findings are supported by the low field leakage analysis, which shows large device to device dispersions. However, the effect of the spike anneal can be minimized if the HfAlOx layer is crystallized prior to the AA. Devices with polysilicon or TiN gate are compared in terms of memory performance and reliability.

The advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.

Several aspects of the integration of diffusion-less junctions in a NMOS and PMOS conventional flows are evaluated. Processes as Solid Phase Epitaxial Regrowth (SPER) or advanced annealing techniques, as flash or laser, demonstrates benefits not only on the 1D junction profiles but also on the transistor characteristics. An optimization of the implants and of the annealing conditions lead to improved or equivalent transistors performance and short channel effects control compared to the conventional spike RTA process. A significant gain in the overlap capacitance could allow for reduced CV/I. Furthermore the junction leakage can be lowered down to the values reached with the conventional spike RTA process.

The impact of material crystallization characteristics on the switching behavior of phase change memory cells has been investigated using finite element simulation. Both a conventional vertical cell and a horizontal line cell have been analyzed, using the widely used Ge2Sb2Te5 (GST) which is a nucleation dominated material for the vertical cell, and Ag5.5In6.5Sb59Te29 (AIST) which is a growth dominated material for the horizontal cell. Nucleation and growth models were implemented for both materials. Both RESET and SET program cycles were simulated. From these simulations, it was shown that the crystallization models gave realistic results for switching voltages, currents and switching times for the two different cell types. It is found that for GST, both nucleation (at lower voltages) and growth (at higher voltages) can play an important role in the crystallization. However, for AIST, crystal growth from non-amorphized crystal regions dominated over nucleation for all program conditions. The high growth rate of AIST moreover is shown to allow much shorter SET times in the line cell compared to that of GST in the vertical cell.

The electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO2 Poly-Si/Ti(C)N/SiO2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO2 and Poly-Si/Ti(C)N/HfO2 gate stacks.