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We demonstrate that ferroelectric memory is very eligible to become a non-volatile cache solution, in particular, in a multimedia storage system such as solid-state disk. It could provide benefits both of performance and of reliability. In performance, a FRAM cache allows us to rid overhead of power-off recovery. Random WRITE performance has been improved by 250%. In assertion of endurance, we investigate acceleration factors to evaluate cycle-to-failure of the ferroelectric memory both in device-level and in capacitor-level. What has been found is that ferroelectric memory cells have 6.0×1014 of the cycle-to-failure at the operational condition of 85 o C and 2.0V. This cycle-to-failure is well above lifetime READ/WRITE cycles of 9.5×1013 in such system. From 2-dimensional stress simulation, it has also been concluded that the number of dummy cells plays a critical role in qualifying the high temperature life tests.
We present the TANOS (Si-Oxide-SiN-Al2O3-TaN) cell with 40 Å-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al2O3) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.
Conventional nonvolatile memories such as Flash and EEPROM memory have successfully evolved toward high density and low cost. Especially, the market and density of flash memories has grown rapidly which leads semiconductor technology. However, there have been concerns about whether this successful progress can be maintained in the future nano era and can satisfy the requirement of diversified future IT market. Flash memories have the advantage of high density with small cell size and by contraries the disadvantage of slow writing speed and limited endurance. This slow writing speed and limited endurance is not aligned with the trend of high speed and reliability for future semiconductor memories.
The future for these conventional nonvolatile memories forces many research groups and companies to develop alternative memories with ideal memory characteristics such as non-volatility, high density, high speed, and low power, which none of the conventional memories can satisfy at the same time.
In this article, I will evaluate the characteristics of future nonvolatile memories such as ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM) and phase change random access memory (PRAM). These memories have been recently evaluated because of the possibility that they can overcome the challenges that conventional memories are facing. Finally we will review critical technology barriers in developing future memory and predict the promising technology to overcome the barriers in conventional and emerging new memories, which will be technology guidelines for future memory development.
With respect to the operation of a Phase-change Random Access Memory (PRAM or PcRAM), we studied the effect of the contact between the electrode metal and the chalcogenide glass, N2 doped Ge2Sb2Te5 in this report. We investigated a change of the resistance-programming current pulse (R-I) curve varying the contact size and the electrode material. Also we tested the surface oxidation of the electrode. We found that the programming current, the resistance of the programmed state (“RESET”) and the erased state (“SET”) were highly dependent on the above parameters. These results are presented and a more effective way to the high density PRAM will be proposed.
An optimized process of Pb(Zr,Ti)O3(PZT) ferroelectric capacitor has been investigated in order to develop a highly scaleable 1T/1C ferroelectric random access memory. The PZT ferroelectric capacitor, Pt/PZT/Pt stack, was formed on the TiO2/SiO2/Si substrate. The PZT thin films were prepared by conventional sol-gel multi-coating method. Physical and electrical properties of the PZT ferroelectric capacitors were characterized by XRD, SEM, TEM and RT6000S, respectively.
It was revealed that the microstructure of PZT thin film is strongly influenced by sol-gel coating process, especially depending on coating methods of the first PZT layer. The second phase was observed in the PZT thin films, which is found to be pyrochlore phase. The size and density of pyrochlore phase were significantly reduced by modifying the coating methods of first PZT layer. Microstructure of PZT thin film capacitors was evaluated in detail along with electrical properties such as remnant polarization, coercive electric field, and dielectric leakage. The sensing Pr window was also introduced for proper sensing margin in IT/1C ferroelectric random access memory. This concept is well verified by 64Kb 1T/1C ferroelectric random access memory.
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