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This work reports the fabrication and characterization of superstrate-type Zn1-xMgxO/CdTe heterojunction solar cells on both CdxSnyO and commercial SnO2:F transparent conducting oxides (TCOs) in which the ZMO and CTO layers are produced for the first time by hollow cathode sputtering. The sputtering is conducted in a reactive mode using metal or alloyed metal targets fitted to a custom-made linear cathode. It is notable that the CdS buffer layer conventionally employed in CdTe solar cells is entirely replaced by the ZMO window layer. The use of ZMO is found to eliminate the blue loss associated with CdS optical absorption and further results in a higher open-circuit voltage. Key parameters were found to be the conduction band offset at the ZMO/CdTe interface and the ZMO thickness. It was discovered that the ZMO exhibits intense photoluminescence even at room temperature. Most of the solar cells were fabricated in the FTO/ZMO/CdTe configuration although CTO/ZMO/CdTe solar cells were also demonstrated. The CTO was produced with an electron mobility of 46 cm2 V-1s-1 without any post-deposition annealing or treatment.
For CdTe there is no real distinction between defects and impurities exists when non-shallow dopants are used. These dopants act as beneficial impurities or detrimental carrier trapping centers. Unlike Si, the common assumption that the trap energy level Et is around the middle of the band-gap Ei, is not valid for thin film CdTe. Trap energy levels in CdTe band-gap can distributed with wide range of energy levels above EF. To identify the real role of traps and dopants that limit the solar cell efficiency, a series of samples were investigated in thin film n+-CdS/p-CdTe solar cell, made with evaporated Cu as a primary back contact. It is well known that process temperatures and defect distribution are highly related. This work investigates these shallow level impurities by using temperature dependent current-voltage (I-V-T) and temperature dependent capacitance-voltage (C-V-T) measurements. I-V-T and C-V-T measurements indicate that a large concentration of defects is located in the depletion region. It further suggests that while modest amounts of Cu enhance the cell performance by improving the back contact to CdTe, the high temperature (greater than ∼100°C) process condition degrade device quality and reduce the solar cell efficiency. This is possibly because of the well-established Cu diffusion from the back contact into CdTe. Hence, measurements were performed at lower temperatures (T = 150K to 350K). The observed traps are due to the thermal ionization of impurity centers located in the depletion region of p-CdTe/n+-CdS junction. For our n+-CdS/p-CdTe thin film solar cells, hole traps were observed that are verified by both the measurement techniques. These levels are identical to the observed trap levels by other characterization techniques.
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