To save content items to your account,
please confirm that you agree to abide by our usage policies.
If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account.
Find out more about saving content to .
To save content items to your Kindle, first ensure email@example.com
is added to your Approved Personal Document E-mail List under your Personal Document Settings
on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part
of your Kindle email address below.
Find out more about saving to your Kindle.
Note you can select to save to either the @free.kindle.com or @kindle.com variations.
‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi.
‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.
High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials.
Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface.
Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs.
Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
We present a one-dimensional simulation study of the capacitance-voltage (C-V) and current-voltage (I-V) characteristics in MOS devices with high mobility semiconductors (Ge and III-V materials) and non-conventional gate stack with high-κ dielectrics. The C-V quantum simulation code self-consistently solves the Schrödinger and Poisson equations and the electron transport through the gate stack is computed using the non-equilibrium Green’s function formalism (NEGF). Simulated C-V characteristics are successfully confronted to experimental data for various MOS structures with different semiconductors and dielectric stacks. Simulation of I-V characteristics reveals that gate leakage current strongly depends on gate stacks and substrate materials and predicts low leakage current for future CMOS devices with high mobility materials and high-κ dielectrics.
We have investigated the impact of a metal gate (TiN) and high-k dielectric (HfO2) on the carrier mobility. We have shown that strong remote Coulomb scattering (RCS) due to charges in the HfO2 layer (either grown by ALD or MOCVD) mostly degrades the mobility at low/medium field. High amount of charges (>1013cm-2) is needed to explain the 30% degradation observed in devices with a thin interface layer. These additional coulombic interactions are effective for bottom oxide up to 2nm. We have developed a RCS model to fully explain the experimental data. The influence of the metal gate is also evidenced. The latter has a significative impact on the Si/SiO2 interface roughness, and may induce some additional coulombic interactions.
Email your librarian or administrator to recommend adding this to your organisation's collection.