To meet the stringent demands of high quality gate performance in advanced devices, a more robust gate dielectric is needed. A stacked structure consisting of thermal oxide and deposited oxide is a potential candidate since it offers certain advantages over single layer oxides such as 1) reduced defect density, 2) reduced stress at the SiO2/Si interface due to stress compensation between the thermal and the deposited oxide, 3) less silicon consumption and 4) reduced thermal budget. In this study, stacked oxides consisting of RTO and RTCVD oxides are characterized. In contrast to other studies which use conventional LPCVD methods to form the top oxide, these stacked oxides have the advantages of rapid thermal and in-situ processing, which produces excellent bulk and interfacial properties. Electrical characterization has shown that these stacked oxides have superior performance compared to single layer furnace or deposited oxides.

As the feature size of MOSFET devices shrink, issues such as thermal budget associated with controlling channel doping profiles and oxide growth kinetics raise concerns about using thermally grown furnace oxides for deep-submicron device applications. To address these concerns, we have developed a new RTCVD oxide process using a gas system of silane and nitrous oxide. The RTCVD oxides are deposited in a lamp-heated, cold wall, RTP system. Deposition rates ranging from 55 Å/min. to 624 Å/min. can be achieved at 800°C with silane nitrous oxide flow rate ratio of 2% and total pressure ranging from 3 to 10 Torr. The results indicate that this RTCVD process can be used to deposit both thin gate and thick isolation insulators for single wafer processing. Deposition rates of the RTCVD oxides exhibit a nonlinear dependence on the total deposition pressure. Electrical characterization of the as-deposited RTCVD oxides shows a mid-gap interface trap density of < 5×1010 eV−1 cm−2 and an average breakdown field of 13MV/cm. AES, RBS and TEM analyses have been used to study surface cleaning effects on the silicon-silicon dioxide interface quality and to determine the chemical composition of the RTCVD oxides. The results show that RTCVD oxides with stoichiometric composition and atomic flat silicon-silicon dioxide interface can be achieved using silane nitrous oxide flow rate ratio of <2%. I-V characteristics and transconductance degradation under hot carrier stress for MOSFET's using as-deposited RTCVD gate oxides have been found to be comparable to those of MOSFET's using thermal gate oxides.

Thin silicon oxynitride (Si-O-N) films have been deposited using low pressure rapid thermal chemical vapor deposition (RTCVD) with silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) as the reactive gases. Structural analysis coupled with a study of deposition conditions indicate that an increase in NH3/N2O flow rate ratios leads to an increased N/O atomic ratio and a decreased Si-O-N deposition rate. Thin film (55-75A) polySi/Si-N-O/Si capacitors and transistors were fabricated for NH3/N2O flow rate ratios from 20% to 100%. Some of the films were subjected to a post deposition anneal at 950°C for 15 seconds in both argon and oxygen. Capacitance voltage measurements indicate a mid-gap interface trap density of ≤ 6 × 1010 eV−1cm−2 for all the films independent of both nitrogen content and post deposition annealing conditions. The transconductance was studied as a function of NH3/N2O flow rate ratio and decreasing peak gm values but improved high field degradation was observed for increased nitrogen content. This is consistent with previous work on nitrided oxides and suggests that the films are under tensile stress. Hot carrier stress at maximum substrate current was performed with the Si-O-N films displaying larger threshold voltage shifts when compared to furnace SiO2 indicating the possible existence of hydrogen related traps.

A combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

Selectively deposited Si0.7Ge0.3 has been investigated as a potential diffusion source for fabricating ultra-shallow junctions in Si. Rapid thermal chemical vapor deposition (RTCVD) was used to selectively deposit Si0.7Ge0.3 on Si using SiH2C12, GeH4, and H2. Both ionimplanted and in-situ doped Si0.7Ge0.3 were considered as a diffusion source for fabricating ultra-shallow junctions. In-situ doping was achieved with B2H6 and PH3 for p-type and n-type doping, respectively. Boron and phosphorus diffusion in ion-implanted Si0.7Ge0.3 was investigated and modeled using SSUPREM4. Diffusion from implanted and in-situ doped Si0.7Ge0.3 in Si was also studied and modeled. Boron diffusivities in Si0.7Ge0.3 were found to be approximately 10 times greater than in Si, while phosphorus diffusivities were over 100 times greater in Si0.7Ge0.3. The faster dopant diffusivities in Si0.7Ge0.3 allow high surface concentration, abrupt diffusion profiles to be formed in Si. Gated, p-n junction diodes with junction depths as shallow as 140Å were fabricated and tested to study the quality of the diffusions from Si0.7Ge0.3.

This paper describes the preparation of silicon-based metal oxide semiconductor, MOS, devices, capacitors and field effect transistors, FETs, using deposited oxide dielectrics. A critical aspect of the device fabrication process is the way the Si-SiO2 interface is formed; e.g., either before, during, or after the oxide deposition. We have studied different methods of fabricating Si-SiO2 heterostructures, and have concluded that the implementation of independently controllable and sequential process steps for (i) interface formation, and (ii) oxide deposition consistently yields MOS devices with electrical properties that are superior to those of devices fabricated under other processing conditions which include specifically interface formation during the oxide deposition.

A combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

Low pressure chemical vapor deposition of polysilicon in a lamp heated rapid thermal processor (RTCVD) has been studied. Polysilicon films were deposited using SiH4 diluted in Ar. Structural characterization of the films was accomplished by transmissionelectron microscopy (TEM), scanning tunneling microscopy (STM), secondary ion mass spectroscopy (SIMS), auger electron spectroscopy (AES) and ultraviolet surface reflectance measurements. Smooth polysilicon films were obtained at deposition temperatures above 700ºC with rms roughness values better than 100 Å. Both p- and n- polysilicon gated MOS capacitors were fabricated using 80 - 200 Å thick gate oxides grown by dry oxidation in a conventional furnace. Polysilicon doping was achieved by ion-implantation and rapid thermal annealing (RTA). Our results show that the electrical properties ofthe capacitors fabricated using RTCVD polysilicon are comparable to those of conventional polysilicon. Dopant diffusion through the gate is a problem for both types of polysilicon and can lead to a degradation of the electrical properties.

Selective depositions of germanium thin films have been investigated in a cold-wall, lamp heated rapid thermal processor. Films were deposited at low pressures (1 Torr-8 Torr) using the thermal decomposition of germane. Selectivity was maintained throughout the temperature range investigated, 350°C-600°C. Growth rates as high as 800 Å/min were obtained at 425°C where deposition is controlled by the surface reactions, making germanium compatible with the throughput requirements of single wafer manufacturing. Three dimensional growth was seen at temperatures above 450°C resulting in a rough surface morphology. Smooth films were deposited below 450°C with the films characterized by two dimensional growth. In this work, germanium is considered as a potential material to fabricate MOS transistors with raised source and drain junctions (UPMOS). Kelvin structures were fabricated to study the effect of the intermediate germanium layer between aluminum and silicon on contact resistance. It is shown that contact resistivity is improved by approximately 17% using an Al/p-Ge/p+-Si structure. In this work, it is also shown that titanium germanide formation can be used as a means of reducing the resistivity of the Ge buffer layer.

We report the first results of direct growth of GaAs by molecular beam epitaxy on nominally (100) oriented silicon with buried implanted oxides. Rutherford backscattering and transmission electron microscopy techniques have been used to characterize these layers. The formation of hillocks and a uniform layer of GaAs in the intervening regions between hillocks have been observed. Microtwins, dislocations and antiphase domain boundaries are the predominant defects observed in these layers.

The diffusion of Sb in heavily doped n- and p-type Si has been studied to determine the activation energies and charge states of the point defects responsible for Sb diffusion. It is shown that neutral point defects, probably Vx, dominate under intrinsic doping conditions. For samples doped with high-concentration As or P backgrounds, Sb diffusion is dominated by a double-negatively charge point defect that causes an n2 concentration-dependent Sb diffusivity. Electric-field effects also are important. The measured diffusion coefficients are Dix = 17.5 exp(−4.05 eV/kT), and Di= = 0.01 exp(−3.75 eV/kT). The activation energies are consistent with diffusion via Vx and V= vacancies. Retarded diffusion of Sb in p+-doped samples with uniform B profiles fits an ion pairing model where Sb+B− pairs form to reduce the flux of Sb atoms.

We have investigated the damage which results from silicon self-implantation for the range of doses from 2E14 to 1E16 cm−2 for temperatures from 82 to 296 K for 150 and 300 keV implants. Cross-sectional TEM was used to evaluate the nature of the amorphous layer. The experimental results were correlated with computer calculated damage distributions using a Monte Carlo simulation program. The depth of amorphous-crystalline interface(s) was evaluated as a function of dose and temperature. An experimental damage energy density curve was constructed. Using the curve, a critical energy density for amorphization, Ec was calculated for the samples implanted at different temperatures. The energy was found to depend on depth and implant energy, and it increased with temperature. A study of a-c interface morphology shows no dependance on temperature within the range considered. Kinetics of dynamic annealing are discussed in conjunction with the above findings.

The geometry, origin, and diffusion along hairpin defects in Si were investigated using TEM and SIMS techniques. The defect that grows from the amorphous-crystalline (a/c) interface following solid phase epitaxy growth front was found to be a perfect dislocation with a/2(101) Burgers vector. Misoriented microcrystallites within the a/c transition region are proposed to be nucleation sites for the hairpin dislocations. The density of the crystallites increases with an overall coarsening of the interface which occurs during dynamic annealing processes stimulated by implantation or post-implantation low temperature annealing. Hairpin dislocations were found to pipe-diffuse boron at much higher rates than bulk processes significantly shifting dopant profiles. The diffusion coefficient of boron pipe diffusion at 1150°C was found to be about 104 times higher than the bulk one.