High resolution transmission electron microscopy (HRTEM) has found extensive use in the semiconductor industry for performing device metrology and characterization. However, shrinking device dimensions (gate oxides are rapidly approaching 10Å) present challenges to the use of HRTEM for many applications, including gate oxide metrology. In this study, we performed HRTEM image simulations of a MOSFET device to examine the accuracy of HRTEM in measuring gate oxide thickness. Length measurements extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy. The effects of specimen tilt, specimen thickness, objective lens defocus and coefficient of spherical aberration (CS) on measurement accuracy were explored for nominal 10Å and 16Å gate oxide thicknesses.
The gate oxide was modeled as an amorphous silicon oxide situated between a gate electrode and substrate, both modeled as single crystal Si(100). Image simulations of the sandwich structure were performed in cross-section (with Si parallel to beam direction) using the multislice approximation for a 200 kV microscope with Cs=0.5mm.