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The influence of low temperature pre-annealing on p+/n ultra-shallow junction was investigated. An ultra-shallow junction was formed by means of B2H6 plasma doping at an energy of 500V. The activation was performed by excimer laser annealing. To study the low temperature annealing prior to laser annealing, furnace annealing at 300°C∼500°C for 5min was performed. Compared with control samples with no pre-annealing, the low temperature preannealing significantly improves junction characteristics, resulting in a reduction of junction depth and a lower leakage current density. A cross-sectional transmission electron microscopy analysis confirmed the lower defect density, which explains the lower leakage current. By optimizing the process conditions, excellent electrical characteristics of the p+/n ultra-shallow junction such as a junction depth of 28nm and a sheet resistance of 250Δ/sq. can be obtained.
This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.
We have investigated the electrical characteristics, junction depth and defect of ultrashallow junctions formed by using a plasma doping procedure. Compared with ultralow energy boron ion implantation at 500eV, the plasma doping process exhibits both a shallow junction depth and a low sheet resistance. The junction depths of the plasma doped samples were 15 nm and 33 nm after annealing for 10s at 900 °C and 950 °C, respectively. For the same junction depth, the sheet resistance of the B2H6 plasma doped sample is an order of magnitude less than that of the 500eV B ion implanted sample. Based on cross-sectional transmission electron microscope (TEM) and deep level transient spectroscopy (DLTS) analysis, the defects formed by the B2H6 plasma doping process can be completely removed by annealing at 950 °C for 10s.
The electrical and reliability characteristics of ultra-thin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si-D bond at the Si/SiO2 interface. This nitridation process of gate dielectric using ND3 has considerable potential for future ultra large scaled integration (ULSI) device applications.
Capacitance-voltage was investigated for amorphous silicon quantum dots (a-Si QDs) embedded in a silicon nitride as a function of dot size and nitride thickness. a-Sci QDs were grown by plasma enhanced chemical vapor deposition. The electron charging was decreased as the dot size was decreased. These results showed that the conduction band shift is larger than the valence band shift as the dot size decreased and, as a result, electrons are easily discharged in a-Si QDs due to the lower barrier height. For high dot-density-sample, the capacitance-voltage curves were also shifted toward the negative voltage direction when a higher forward bias was applied at forward condition due to the transfer of electrons trapped in the a-Sci QDs from the a-Sci QDs near Si substrate to those near the top metal.
In this paper, we report a process for the preparation of high quality amorphous tantalum oxynitride (TaOxNy) via ammonia annealing of Ta2O5 followed by wet reoxidation for use in gate dielectric applications. Compared with tantalum oxide(Ta2O5), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We confirmed nitrogen incorporation in the tantalum oxynitride (TaOxNy) by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness of less than 1.6nm and a leakage current of less than 10mA/cm2 at -1.5V. Compared with NH3 nitridation, nitridation of Ta2O5 in ND3 improve charge trapping and charge-to-breakdown characteristics of tantalum oxynitride.
We present a novel gate oxidation process using D2O (deuterium oxide) as an oxidizing gas. The electrical and reliability characteristics of ultrathin gate oxide grown in D2O ambient have been investigated. Compared with a control oxide grown in H2O, a oxide grown in D2O exhibits a significant reduction of charge trapping and interface state generation. Based on a secondary ion mass spectroscopy (SIMS) analysis; we found a deuterium rich-layer at the Si/SiO2 interface. The improvement of electrical and reliability characteristics can be explained by the deuterium incorporation at the Si/SiO2 interface.
We have compared the electrical characteristics and the depth profile of an ultrashallow junctions formed by boron implantation at 0.5 keV and BF2 implantation at 2.2 keV. The modeling of the boron profile was performed using the Monte Carlo method for an as-implanted profile and the computationally efficient method for transient-enhanced diffusion. A junction depth of BF2 is shallower than that of boron after annealing. HF dipping prior to rapid thermal annealing causes a significant loss of dopant and high sheet resistance. Considering the 0.1 νn metal-oxide-semiconductor field-effect-transistor (MOSFET) application, the optimizations of implantation and annealing conditions are necessary to satisfy the requirement ofjunction depth and sheet resistance.
Selective chemical etching and atomic force microscope (AFM) examination has been performed to delineate two-dimensional (2-D) dopants profiles of p/n-type well and junction areas. Selectivity strongly depended on the types of dopants and the ratio of etching solutions. Calibration showed that the carrier concentrations in both p/n-type regions could be delineated down to a level of ∼1×1017/cm3. The AFM-induced profiles were compared with the calculated data provided by the 2-D process simulators such as TRIM and SUPREM-IV.
Self-aligned silicide (salicide) formation of epitaxial CoSi2, using a Co/Ti bilayer, on linear oxide (SiO2) patterned (100)Si substrate has been investigated. Rapid thermal annealing (RTA) at 550°C resulted in the lateral encroachment of silicide in the Si under the edge of the oxide. After RTA at 900°C, even though an epitaxial CoSi2 layer was formed on the Si substrate, defects such as lateral encroachment and voids were generated under the edge of the oxide. It was found that such defects lead to device failure due to the deterioration of the gate oxide and the shallow junction.
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