Because of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.

The use of carbon nanotubes (CNT) as interconnects in future integrated circuits (IC) is being considered as a replacement for copper. As this research needs also innovative metrology solutions, we have developed a combined approach for the plane-view analysis of CNT integrated in contact holes where transmission electron microscopy (TEM) enables the quantitative measurement of density and structure of the CNT and where scanning spreading resistance microscopy (SSRM) is used to electrically map the distribution of the CNT. This paper explains the used methodologies in detail and presents results from 300 nm diameter contact holes filled with CNT of 8-12 nm in diameter and a density of about 2 x 1011 cm-2.

The three-dimensional (3D) distribution of carbon nanotubes (CNTs) grown inside semiconductor contact holes is studied by electron tomography. The use of a specialized tomography holder results in an angular tilt range of ±90°, which means that the so-called “missing wedge” is absent. The transmission electron microscopy (TEM) sample for this purpose consists of a micropillar that is prepared by a dedicated procedure using the focused ion beam (FIB) but keeping the CNTs intact. The 3D results are combined with energy dispersive X-ray spectroscopy (EDS) to study the relation between the CNTs and the catalyst particles used during their growth. The reconstruction, based on the full range of tilt angles, is compared with a reconstruction where a missing wedge is present. This clearly illustates that the missing wedge will lead to an unreliable interpretation and will limit quantitative studies.

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

The nitride-based SONOS cell, for its excellent scalability and process simplicity, is the candidate to push the scaling roadmap for FLASH memories beyond the limit imposed on floating-gate memories by the electrostatic interference between adjacent cells. The traditional SONOS cell consists of a nitride layer (the storage element) encapsulated by two SiO2 layers which isolate the nitride layer from the Si substrate and the poly-Si gate (Poly-Si/SiO2/Si3N4/SiO2/c-Si). However, the thick tunnel oxide necessary to meet the retention requirements imposes a severe limit on the erase performance because of the erase saturation phenomenon. One possibility to guarantee both the erase and the retention performance is the replacement of the top SiO2 layer with materials of higher dielectric constant (high-k dielectric). The presence of a high-k dielectric reduces the electric field across the top dielectric, thus decreasing the unwanted parasitic electron injection from the gate during the erase operation. This will allow the cell to erase deep so to meet a basic requirement for Gigabit multilevel NAND memories. The introduction of high-k materials in the SONOS stack is unfortunately not straightforward. One problem is the Fermi-level pinning at the poly-Si/high-k interface. Another problem is the morphological changes the high-k material undergoes during the device fabrication thermal budget. These changes can modify the k-value and affect the band offset between gate and high-k material. The results may, in both cases, be the decrease of the barrier for electron injection from the gate and, as a consequence, the deterioration of the erase performance. In this paper we study the effect of gate material and of the morphological transformation associated with the high-k post deposition anneal on the erase and the retention behaviour of nitride-based cells. Two different high-k dielectrics are investigated: Al2O3 (which has already been found to be able to significantly improve the erase operation, guaranteeing at the same time excellent endurance and sufficient bake retention) and HfAlO. We show that both for Al2O3 and HfAlO a trade-off exists between erase and retention, higher PDA temperatures being beneficial for erase but detrimental for retention. We also discuss the effect of Fermi level pinning and poly-Si depletion on the erase behaviour and compare the erase performances of several PVD- and AVD-deposited metal gates.

Establishing a cost-effective technology for the metallization of through-Si vias (TSV) is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a void-free TSV fill, but also short filling time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the following processing steps (e.g. chemical mechanical polishing, CMP). In this paper we report on Cu plating of TSV-s with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits.

The potential use of carbon nanotubes (CNT) as interconnects requires also new characterization approaches as the existing ones are optimized for three-dimensional materials and do not work for inherently one-dimensional structures like CNTs. Therefore, we have developed a so-called pick-and-place process which allows to remove an individual CNT from a specific site and to place it at another location for further analysis. The approach is based on nanomanipulation combined with scanning electron microscopy (SEM). This paper presents the pick-and-place concept and explains the different steps required for its successful application. We further demonstrate its power by characterizing individual CNTs using transmission electron microscopy (TEM) and atomic force microscopy (AFM). The developed pick-and-place approach overcomes the challenge of site-specific analysis of CNT interconnects and strongly facilitates the routine analysis of CNTs.

Ultrathin lanthanide (Nd, Pr, Eu, Sm) oxide films with functional dielectric properties down to 3.3 nm thickness were deposited by aqueous chemical solution deposition (CSD) onto hydrophilic SiO2/Si substrates. Precursor solutions were prepared from the oxides via an intermediate, solid Ln(III)citrate. A film heat treatment scheme was derived from thermogravimetric analysis of the precursor gels, showing complete decomposition by 600 °C. Crystalline phase formation in the films depended on the lanthanide, annealing temperature, and citric acid content in the precursor. Through variation of the precursor concentration and number of deposited layers, thickness series of uniform films were obtained down to ∼3 nm. The film uniformity was demonstrated both by atomic force microscopy and cross-section transmission electron microscopy. The lanthanide oxide films possessed good dielectric properties. It was concluded that aqueous CSD allows deposition of uniform ultrathin films and may be useful for the evaluation of new high-k candidate materials.

We have studied strained Si layers grown on Si1-xGex virtual substrate (VS) by high-resolution transmission electron microscopy (HRTEM). Aberration-corrected HRTEM coupled with geometric phase analysis (GPA) provides precise measurements of strain. Different parameters are investigated: the VS composition (x=20, 30, 40 and 50%) and the s-Si layer thickness. Finite element method simulations confirm our measurements. Measurements and simulations lead to the conclusion that the strain state of the deposited layer is independent of the layer thickness. We apply the technique to measuring strains in the channel region of a p-MOSFET and show that the technique is a promising metrological tool for nanoelectronic devices.

Boron diffusion and defect evolution during sub-millisecond (ms) laser annealing with partial SPER are investigated using secondary ion mass spectrometry and transmission electron microscopy. Boron diffusivity enhancement in amorphous-Si is observed during partial SPER at 550 °C. It is shown that boron diffusion during the laser annealing process is a 2-step diffusion (SPER + Laser). The depth of the amorphous layer affects the dopant activation behavior. During sub-ms laser annealing, end-of-range defects are formed and show an evolution behavior. {311} defects cannot completely transfer to dislocation loops after 1300 °C laser annealing. It is considered that the thermal budget of sub-ms laser is too small for full defect evolution. Atomistic diffusion modeling using a kinetic Monte Carlo method can explain the defect behavior during laser annealing.

Si based nanostructures such as Ge or Si1-xGex dots embedded in Si receive a lot of attention. This interest is driven by the reduction of device sizes as well as by their possible use in opto-electronic applications, as a possible solution to improve the radiative light emission. In this paper we give a detailed overview of the growth kinetics as observed for Ge growth in a standard production oriented chemical vapor deposition system. The island morphology and density are controlled by varying the growth conditions or by applying a thermal anneal after the island growth. Island densities up to 2.3x1010 cm−2 have been obtained for depositions at 650°C. With increasing deposition time, the usual change-over from monomodal to bimodal island distribution is pointed out and this change-over depends on the critical island diameter, which decreases with decreasing growth temperature. Applying a thermal budget after the island growth initiates Ge surface diffusion and Si diffusion from the substrate through the islands. This results in an enhancement of the island diameter and height, and also in a reduction of island density. Furthermore, depending on the island distribution after Ge deposition, a transition from pyramid to dome or visa versa is observed after the in-situ anneal. Optical device structures require a Si cap layer. However, Si capping at 700°C, leads to a nearly total dissolution of small islands and a truncation of bigger dome-shaped islands. This can be prevented by reducing the deposition temperature and by changing the Si gas source. Clear island luminescence, is observed up to 200K and lies in the spectral range of 1.35-1.50μm, which is interesting from the point of view of applications. In particular, this shows the potential of this material system for opto-electronic device applications. In spite of the fact that the observed PL intensity is comparable to the best reported values, we could further enhance it by a thermal treatment in a H2 plasma.

Mg is one of the elements that are regarded as having a beneficial effect on the Al electromigration (EM) lifetime. In this paper, we compare the EM behavior of 0.4 μm wide passivated Al-1%Mg-0.5%Cu, Al-0.5%Cu and Al-l%Si-0.5%Cu lines. Plan-view transmission electron microscopy and focused ion beam imaging reveal that Al(MgCu) film undergoes bimodal grain growth. Auger electron spectroscopy and secondary ion mass spectrometry show a strong surface segregation and a severe bulk depletion of Mg. Additionally the line-width dependence of the rate of the resistivity decay during aging shows also a different behavior for Al(MgCu) compared to Al(Cu) and Al(SiCu). All these findings are consistent with the EM results that Al(MgCu), processed with our experimental conditions, has both the lowest median time to failure and deviation in time to failure. The results are discussed in the light of the effect of Mg addition on the microstructure and of the great surface activity of Mg.

PtSi is one of the most used silicides in infrared Schottky barrier detectors due to its low Schottky barrier to p-type Si ( Øb ∼ 0.23 eV). Control of the thickness and uniformity of the silicide layer is fundamental for a good infrared detector performance, since the silicide thickness has to be in the range of 3 to 8 nm. Such thin layers are usually made by evaporation of Pt followed by a furnace annealing. We will show different approaches for fabrication of utra-thin PtSi layers. In all of the processes, high-vacuum sputtering is used for Pt deposition and the silicidation is performed in a rapid thermal annealing system. Smooth and uniform Pt Si layers down to 3 nm thick are formed in this way. It will be shown that the controllability of the thickness during sputter deposition is not a critical issue and the deposition process has a large process window. Moreover, when taking an optimal approach, a large process window can also be found for the RTA step. The implementation of these approaches for device fabrication and some electrial results of diodes made with them will also be presented.

Epitaxial CoSi2(100) layers in the thickness range of 20 to 50 nm have been formed by reactive deposition epitaxy (i.e. Co deposition onto a hot Si substrate) without the use of either a template or an intermediate Ti layer. It is explained how growth parameters such as the deposition rate and substrate temperature are crucial in determining the epitaxial nature of the silicide. According to this model, good CoSi2/Si(100) alignment is only achieved when very low deposition rates are used (0.1 Å/s or less), combined with relatively high substrate temperatures during deposition (∼ 600°C or higher). Using these conditions, highly strained, continuous CoSi2 layers with a channeling minimum yield of χmin = 9% could be formed. Using higher rates and/or lower deposition temperatures, an increasing fraction of misoriented CoSi2 grains is presumed from backscattering/channeling and x-ray experiments, the nature of which is under investigation with plan view and cross sectional transmission electron microscopy.

Three regimes of HF-H2O vapor etching of oxide can be distinguished, viz. a gas phase, an adsorption and a condensation regime with gas phase etching behaving distinctily different in terms of etch rate and surface passivation properties. Integration of a vapor etch process in a vacuum-controlled, leak-tight cluster tool equipped with vertical reactor LPCVD and oxidation modules offers important thin film interface engineering capabilities; significant process control improvement is achievable in critical device technologies, such as formation of poly-contacts, poly-emitters and NO capacitors.

The structural characterization of the oxygen related lattice defects formed under different thermal cycling conditions is discussed. The present understanding on the nature of rod-like defects and oxide precipitates is reviewed. Attention is given to the whole lattice defect spectrum which is induced by the oxygen precipitation. The influence of carbon and dopants on the defects is discussed.

In this paper we present a rapid and highly precise plan view and cross-section specimen preparation technique for the localized thinning of semiconductor devices for TEM investigation. No special equipment except the commercially available one is required. Crosssection preparation takes about 6 hours, while plan view takes about 4 hours. Prespecified areas of 0.6 μm wide and 10 μm long can easily be thinned with transparency for CTEM and HREM. Using an iterative ion milling procedure allows to scan a complete device in HREM.