Low-k dielectrics are currently starting to replace SiO2 in advanced on-chip interconnects. Being low surface energy materials, a major concern for the integration of such dielectrics in Cu damascene processes is given by adhesion failure at the interfaces of the low-k films with cap or liner layers during Chemical Mechanical Polishing (CMP). A cross-comparison between interface fracture energies as measured through four-point bending, CMP experiments and stress fields computed by Finite Element Modeling, shows that it is not possible to predict failures by setting a ‘universal’ threshold on adhesion strength.
In particular, we report on the critical role of CMP –induced shear stress on the onset of interface debonding, and the way the shear load is transmitted to the critical interfaces. The top-down load transmission depends on the position of the weak interfaces, and on the way the intermediate films in the stack can confine such load through their thickness and mechanical (elastic and plastic) properties.