Ternary electroless nickel, NiXP, films were produced by adding salts of Mo, Re, Tl, Cu, W, Co, Fe, Zn, and Mn to conventional electroless Ni baths and subsequently reacted with Sn-3.5Ag solder. From the full width at the half maximum (FWHM) data, as-plated NiXP films can be categorized into two groups: one is close to the FWHM value of nanocrystalline Ni5P film and the other is close to amorphous Ni9P film. Alloying elements in the electrolessly plated under-bump metallurgy that effectively suppressed intermetallic compound (IMC) spalling were Mn, Zn, Re, Fe, and W, whereas Tl exacerbated spalling. The roles of Cu, Mo, and Co were less clear due to a lack of data. Based on scanning electron microscopy observations, a spalling map was presented, which showed elemental demarcation lines of IMC spalling in the X-P coordinates.

Effects of tungsten (W) addition to the electroless Ni(P) under bump metallization (UBM) on the solder joint reliability were investigated by preparing Ni–xW–5P and Ni–xW–9P films. Characteristics of the NiWP films, interfacial reaction with Sn–3.5Ag solder, and the impact resistance of solder joints was investigated by conducting differential scanning calorimetry, x-ray diffraction, scanning electron microscopy, transmission electron microscopy (TEM), and drop tests. Tungsten increased the thermal stability of the film and raised the crystallization temperature, but the crystallinity decreased with the W content in the film. The drop impact resistance of the Sn–3.5Ag/Ni–xW–9P joints was improved remarkably with the W content in the UBM, which was a direct consequence of the elimination of Ni3Sn4 spalling from the UBM. Additions of W up to 16 wt.% did not suppress intermetallic compound (IMC) spalling completely, but 22 wt.% W did up to 4 reflows, which increased the number of drops to failure (Nf) from 50 to over 300. TEM study showed the presence of an amorphous (Ni,W)3P layer between Ni3Sn4 and the original Ni–22W–9P UBM.

System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated.

A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

In this paper we investigated a feasibility of Y2O3 films as a buffer layer of MFIS (metal ferroelectric insulator semiconductor) type capacitor. Buffer layers were prepared by two-step process of a low temperature film growth and subsequent RTA treatment. Investigated parameters are given as substrate temperature, O2 partial pressure, post-annealing temperature, and suppression method of interfacial SiO2layer generation. By employing an ultra thin Y pre-metal layer, unwanted SiO2 layer generation was successfully suppressed at an interface between the buffer layer and Si substrate. By using two-step process, we improved the leakage current density of Y2O3 films by 2 orders and the Dit as low as 8.72×1010 cm−2eV−1. For a substrate temperature above 400°C and O2 partial pressure of 20%, we observed cubic Y2O3 phase domination in XRD spectra. We achieved 1.75% lattice mismatch between Y2O3 film and silicon substrate. Y2O3 buffer layer for a single transistor FRAM exhibited optimal properties when it was grown at 400°C with 20% O2 partial pressure then RTA treatment at 900°C in oxygen ambient.