Doping of thin body Si becomes very essential topic due to increasing interest of forming source/drain regions in fully depleted planar silicon-on-isolator (SOI) devices or vertical Fin field-effect-transistors (FinFETs). To diminish the role of the short-channel-control-effect (SCE) the Si layers thicknesses target the 10 nm range. In this paper many aspects of thin Si body doping are discussed: dopant retention, implantation-related amorphization, thin body recrystallization, sheet resistance (Rs) and carrier mobility in crystalline or amorphized material, impact of the annealing ambient on Rs for various SOI thicknesses. The complexity of 3D geometry for vertical Fin and the vicinity of the extended surface have an impact on doping strategies that are significantly different than for planar bulk devices.

FinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

A new carbon-interstitial clustering model has been developed. The model has been implemented into the process simulator Sentaurus Process. Model parameters have been calibrated using fundamental marker layer experiments. B diffusion retardation in the C doped layer as well as Sb diffusion enhancement in the region close to a layer with high C concentration are successfully simulated. The calibrated model has been applied to simulations of ultra-shallow junction formation by high dose P-C and B-C co-implantation. It is assumed that, in regions which are amorphized by ion implantation and recrystallized by solid phase epitaxy, C is in the substitutional state right after the recrystallization. In contrast, in non-amorphized regions, C is assumed to be in clusters at the beginning of thermal annealing. A good agreement between simulation and experimental results has been achieved. The dependence of dopant diffusion on implanted C dose and spike annealing temperature has been reproduced.

The advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.

Within this paper we have demonstrated the unique capability of scanning spreading resistance microscopy (SSRM) in order to evaluate and optimize the recent approaches towards the formation of advanced p-MOS devices. As shown in this paper, such an optimization requires a detailed 2D-analysis on completely processed devices as two-dimensional interactions may cause (unexpected) lateral diffusion and (de) activation of underlying profiles. Emphasis will be on junction formation using Ge- pre-amorphization and carbon based cocktail implantation coupled with activation based on solid phase epitaxial regrowth and/or millisecond laser anneal. In the case of a Ge-pre-amorphization implant followed by solid phase epitaxial regrowth, SSRM shows an obvious relationship between the presence of defects in the end of range region and halo implant de-activation. Based on the quantified 2D-profiles we can extract the lateral and vertical junction depths as well as the lateral and vertical abruptness of the extension region. A drastic reduction of the lateral diffusion for the cocktail implant versus the standard reference devices with classical spike annealing is eminent. At the same an important reduction of the lateral diffusion of the source/drain implants (HDD) under the spacer can be seen. The SSRM results also highlight the impact of different activation mechanisms on the channel implants (in particular on the shape of the halo pockets).

As extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.

This work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI.

We present B junction extensions that are extremely abrupt and shallow manufactured by amorphization, C co-implantation and conventional rapid thermal annealing (RTA). Resulting junctions have abruptnesses of 2 nm/dec better than as-implanted profiles. The most shallow B junction that has been manufactured is 15 nm deep and Rs = 626 Ω/sq. Successful implementation of these junctions is straightforward for P-MOS 30 nm gate length devices.

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

Making use of SPER (Solid Phase Epitaxial Regrowth) As and B deep source/drain junctions with high activation can be obtained at temperatures below 700°C. However, higher thermal budget is required to regrow and activate the dopants in the poly gates. Low junction leakage and low contact resistance can be obtained for Ni-silicided As and B SPER junctions making use of deep As and B implants. Because of the low thermal budget source/drain junctions obtained by SPER are an attractive alternative to conventional spike annealed junctions for technologies making use of metal gates.