This retrospective cohort study examined prosocial skills development in child welfare-involved children, how intimate partner violence (IPV) exposure explained heterogeneity in children’s trajectories of prosocial skill development, and the degree to which protective factors across children’s ecologies promoted prosocial skill development. Data were from 1,678 children from the National Survey of Child and Adolescent Well-being I, collected between 1999 and 2007. Cohort-sequential growth mixture models were estimated to identify patterns of prosocial skill development between the ages of 3 to 10 years. Four diverse pathways were identified, including two groups that started high (high subtle-decreasing; high decreasing-to-increasing) and two groups that started low (low stable; low increasing-to-decreasing). Children with prior history of child welfare involvement, preschool-age IPV exposure, school-age IPV exposure, or family income below the federal poverty level had higher odds of being in the high decreasing-to-increasing group compared with the high subtle-decreasing group. Children with a mother with greater than high school education or higher maternal responsiveness had higher odds of being in the low increasing-to-decreasing group compared with the low stable group. The importance of maternal responsiveness in fostering prosocial skill development underlines the need for further assessment and intervention. Recommendations for clinical assessment and parenting programs are provided.

This article attempts to outline the most important assumptions of the work of Kokyu Studio led by Przemysław Błaszczak and Joanna Kurzyńska and based at the Grotowski Institute in Wrocław in Poland. The Studio’s educational and artistic programme is founded on the idea of a ‘place of practice’, which captures the philosophical, practical, aesthetic, and ethical horizon of the activities common to all members of the Studio. The regularity of practice, exposure to long working processes, and the improvement of the quality of movement, which are rooted in several traditions and methods of work, allow practitioners to study their own development and integrate various sources of knowledge. Reflections here also ask questions about the place and application of such a model of work in the context of contemporary challenges for actor-performer training.

We apply a thin luminescent downshifting (LDS) coating to a hydrogenated amorphous Si (a-Si:H) solar cell and study the mechanism of possible current enhancement. The conversion material used in this study converts wavelengths below 400 nm to a narrow line around 615 nm. This material is coated on the front of the glass of the a-Si:H solar cell with a glass/TCO/p/i/n/Ag superstrate configuration. The initial efficiency of the solar cell without the LDS coating is above 9.0 % with open circuit voltage of 0.84 V. Typically, the spectral response below 400 nm of an a-Si:H solar cell is weaker than that at 615 nm. By converting ultraviolet (UV) light to red light, the solar cell will receive more red photons; therefore, solar cell performance is expected to improve. We observe evidence of downshifting in reflectance spectra. The cell Jsc decreases by 0.13 mA/cm2, and loss mechanisms are identified.

We report our progress toward high-performance hydrogenated amorphous silicon (a-Si:H) solar cells fabricated in NREL's newly installed multi-chamber film Si deposition system. The a-Si:H layers are made by standard radio frequency plasma-enhanced chemical vapor deposition. This system produces a-Si:H p-i-n single-junction devices on Asahi U-type transparent conducting oxide glass with >10% initial efficiency. The importance of the p-layer to the cell is identified: it plays a critical role in further improving cell performance. Our optimization process involves changing p-layer parameters such as dopant levels, bandgap, and thickness in cells as well as applying a double p-layer. With the optimized p-layer, we are able to increase the fill factor of our cells to as high as 72% while maintaining high open-circuit voltage.

Polycrystalline Cd1-xMgxTe (CMT) thin films are a potential absorber material for two-junction thin-film tandem solar cell applications because the desired top cell bandgap range of 1.6 to 1.8 eV is readily obtained using CMT with only small resultant changes in the lattice constant from that of CdTe. Tandem devices require the top cell to have a transparent back contact to transmit the sub-bandgap spectrum to the bottom cell. Sputtered Cu-doped ZnTe (ZnTe:Cu) thin films, which offer potential as a transparent back contact interface layer, have been used successfully in CdTe devices. We apply ZnTe:Cu back contacts to CMT devices to continue development toward a transparent top cell. We describe the effects of depositing ZnTe:Cu at different temperatures and with different Cu contents on the net acceptor concentration, minority carrier lifetime, and device performance. We present here the highest reported CMT device efficiency of 9.6% at a bandgap of 1.57 eV.

Several wet-processing steps are used in fabricating high-efficiency CdTe/CdS solar cells. These steps can hinder in-line processing; thus, developing an all-dry processing option is attractive for a manufacturing-friendly process. In this study, we systematically modified the baseline process used in our laboratory to replace CdS deposited by chemical-bath deposition (CBD) with sputter-deposited CdS and Cu-doped graphite paste back-contact with Cu-doped ZnTe deposited by radio-frequency sputtering. In addition to CdTe deposited by close-spaced sublimation, we also used conventionally evaporated CdTe. The results show that replacing only CBD CdS with oxygenated CdS deposited by sputtering produces devices with performance comparable to baseline devices if the front bilayer SnO2 is replaced by a Cd2SnO4/ZnSnO alloy. Replacing the graphite paste back-contact with sputter-deposited Cu-doped ZnTe resulted in device performance comparable to baseline devices. Incorporating both dry processing steps gave performance comparable to the devices with sputtered CdS with a SnO2 front contact. We used capacitance-voltage and minority-carrier lifetime measurements to analyze the factors affecting device performance and we present the results here.

A set of 24 identically made CdS/CdTe devices were subjected to accelerated lifetime testing (ALT) under open-circuit bias, 1 sun illumination, and temperatures of 60, 80, 100, and 120 °C. A total of 6 identical devices were tested for statistical purposes at each temperature. Current density-voltage (JV) measurements were made on stressed cells for up to 2000+ hours. Device performance parameters were calculated as a function of temperature and stress time using discrete element circuit models. Forward current behavior was represented by two parallel diodes to simulate recombination currents in the quasi-neutral (QNR) and space-charge (SCR) regions. Backcontact behavior was studied using a parallel combination blocking diode and shunt conductance. A systematic pattern of degradation was apparent with increased stress temperature. At 60 °C, degradation associated with the CdTe/backcontact dominates. At temperatures above 80 °C, greater losses in fill factor (FF) and open-circuit voltage (Voc) were observed. Recombination current modeling of JV data attributes this to increased space-charge recombination. Calculated diffusion lengths based upon an Arrhenius-derived activation energy of 0.63 eV in this temperature-range suggests Cu diffusion into the SCR is mechanistically responsible for the observed increased recombination, and decreased Voc and FF. At lower temperatures (60 to 80 ºC), degradation was considerably slower with a measured activation energy of 2.9 eV.

We present our work on development of Cd1-xMgxTe (CMT) polycrystalline thin film for solar cells for tandem cell applications. CMT thin films were fabricated by co-evaporation of CdTe and Mg at a substrate temperature of 400˚C. The spatial separation of the two sources resulted in a compositional gradient, which allowed the deposition of a wide range of compositions from fewer runs. Stable films for compositions up to x=0.73 were fabricated. The structural analysis showed that the as-deposited films have a sphalerite structure and are preferentially oriented in the <111> direction, and the lattice constant varies linearly with composition. Optical analysis of the samples shows that the optical bandgap varies linearly with composition. The optical absorption coefficient of the alloy films for the entire composition range (up to x=0.73) is over 6×104/cm-1 for energies above the bandgap, indicating a direct-gap semiconductor. We have fabricated solar cells using these films with the following structure: glass / SnO2 / CdS / CMT / back contact. Using the same processing conditions used for CdTe solar cells, the device efficiency was less than 2%. With modified contact processing, we were able to improve efficiencies to over 5%. Post-deposition chloride heat-treatment in oxygen ambient resulted in partial dissociation of the CMT alloy and loss of Mg. With modified chloride processing, we were able to reduce alloy decomposition and further improve the efficiencies. We have obtained devices with open-circuit voltages of up to 845 mV and efficiencies of 8% for CMT devices with a bandgap in the range of 1.6-1.62 eV which are highest reported values for CMT alloys.

Polycrystalline thin-film CdTe is one of the leading materials used in photovoltaic solar cells. One way to improve device performance and stability is through understanding how various process steps alter defect states in the CdTe layer. Low-temperature photoluminescence (PL) studies show a 1.456-eV PL peak in single-crystal CdTe that is likely due to a Cui-OTe defect complex. A similar peak, observed in as-deposited glass/SnO2:F/CdS/CdTe thin-film structures, strongly suggests a common origin. The 1.456-eV peak is also seen in a thin-film sample after performing the CdCl2 treatment needed for high efficiencies.

We have developed high current density thin-film silicon n-i-p diodes for low cost and low temperature two-dimensional diode-logic memory array applications. The diodes are fabricated at temperatures below 250°C on glass, stainless steel, and plastic substrates using hot-wire chemical vapor deposition (CVD). The 0.01-mm2 standalone diodes have a forward current-density (J) of near 10 kA/cm2 and a rectification ratio over 107 at ±2 V. The 25 μm2 array diodes have J > 104 A/cm2 and rectification of 105 at ±2V. On plastic substrates, we have also used plasma-enhanced CVD to deposit 10-μm diameter diodes with J ˜ 5 x 104 A/cm2. We found that the use of microcrystalline silicon (μc-Si) i- and nlayers results in higher current-density diodes than with amorphous silicon. Reducing the diode area increases the forward current density by lowering the voltage drop across the external series resistances. A prototype diode array memory based on 10-micron devices was successfully demonstrated by monolithically integrating diodes with a-Si:H switching elements. High current density diodes have potential applications in a variety of large area, thin-film electronic devices, in addition to a-Si:H-based memory. This could widen the application of thin-film silicon beyond its present industrial applications in thin-film transistors, solar cells, bolometers and photo-detectors.