For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

The results of an in situ transmission electron microscopy study of the formation of Co-silicides on patterned (001) Si substrates are discussed. It is shown that the results of the in situ heating experiments agreed very well with the data based on standard rapid thermal annealing experiments. Fast heating rates resulted in better definition of the silicide lines. Also, better lines were obtained for samples that received already a low-temperature ex situ anneal. A Ti cap layer gave rise to a higher degree of epitaxy in the CoSi2 silicide.

The relationship between silicide thickness, sheet resistance and silicon consumption is experimentally checked for Co-disilicide and Ni-monosilicide. The reverse bias leakage current of shallow Ni-silicided and Co-silicided square diodes is compared for varying junction depth and varying silicide thickness. A lower reverse bias leakage current is obtained for a Ni-silicided shallow junction as compared to its Co-silicided counterpart. This can be attributed to the reduced silicon consumption. The Ti cap does not play an active role during the Ni-silicidation of narrow active area and poly lines. It is shown that a Ni-silicidation process is scalable without Ti cap.

When scaling down the MOS technology, the increasing local mechanical stress induced during the Ti- and Co/Ti silicidation can exceed the critical shear stress on the {111}<110> active glide system in the silicon substrate. This results in the heterogeneous nucleation of 60° dislocations in the silicon substrate underneath the silicide line. In the case of an undoped silicon substrate, these dislocations nucleate at the edge of the silicide lines and are parallel with the [110] oriented line edge. This paper will investigate the effects of As and BF2 junction implantation and implantation defects on the stress developed during the silicidation reaction and on the nucleation and growth of the stress induced 60° dislocations in the silicon.

In this paper, a detailed analysis of silicide induced stress is presented. Micro-Raman spectroscopy measurements of the silicide induced stress in the silicon substrate are combined with simulations by Finite Element Modeling down to 0.1 μm MOS technologies. It is shown that the scaling possibilities of TiSi2 and of CoSi2 are both hampered by the increasing silicide stress, which can even result in the generation of dislocations in the silicon substrate. Because of the difference in material properties between TiSi2 and CoSi2, TiSi2 induces a higher stress in the silicon substrate than CoSi2. It is also proven that the silicide induced stress affects the performance of transistors and diodes. Therefore, the mechanical characteristics related to the silicide formation become a critical parameter in the optimization of the silicide for sub-0.25μm MOS technologies.

The introduction of rapid thermal processing for silicide formation has triggered a lot of research to temperature uniformity and reproducibility in RTP systems. In addition to the temperature, the ambient control is to be taken into account. Although gasses are specified to a low level of contaminants, the RTP step needs to be optimised for optimal contaminant reduction. Besides, the process wafer itself is a source of contamination.

In this paper an overview will be given of the role of RTP ambient on the silicidation processes. The effect of the wafer on ambient purity will be highlighted. It will be shown that the use of a reactive capping layer during silicidation represents an adequate solution for both sources of contamination.

The primary objective of this work is to carry out a combined experimental and numerical investigation of the mechanical stress induced during the Ti-silicidation of narrow lines spaced by a Poly Buffered Local field oxide. Therefore micro-Raman spectroscopy (μRS) measurements of local mechanical stress are combined with simulations by Finite Element Modeling (FEM). Numerical determination of the local stress in the Si-substrate by means of FEM becomes more and more important when scaling down the device dimensions because the spatial resolution of μRS is limited at about 1μm and because the stress in the Si-substrate underneath silicided lines can not be detected using pRS unless the silicide is very thin. The Finite Element analysis was done using SYSTUS and involves a two dimensional plane strain thermo-elastic formulation. A good agreement was obtained between the FEM simulations and the μRS data for line widths above 1Bm making the extrapolation of the FEM to line widths smaller than I1m an attractive alternative for μRS.