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Impact of ultra-thinning on DC characteristics of MOSFET devices

Published online by Cambridge University Press:  15 January 2002

S. Pinel ,
F. Lépinois ,
A. Cazarré ,
J. Tasselli ,
A. Marty  and
J. P. Bailbé
S. Pinel
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
F. Lépinois*
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
A. Cazarré
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
J. Tasselli
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
A. Marty
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
J. P. Bailbé
Affiliation:
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France
*
lepinois@laas.fr
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Abstract

The purpose of this paper is to highlight the impact of thinning on low and high levels DC characteristics of SmartMOS LDMOS devices. Both subthreshold and saturation current voltage deviations are discussed.

Keywords

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 17 , Issue 1 , January 2002 , pp. 41 - 43
Copyright
© EDP Sciences, 2002

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References

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A.C. Acheu, Dow Deutschland Inc., private communication.