A new type of silicon-based Vertical MOSFET concept is presented - Single-Device CMOS (SD-CMOS) - in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions . SD-CMOS offers new possibilities for CMOS integration schemes that are simpler - requiring only 5 masks for the “Front- End” - and less costly to manufacture, than any integration scheme requiring the fabrication of two devices with opposite polarities.
In epitaxially grown Vertical MOSFETs, the source, channel and drain can have atomically sharp interfaces, well controlled doping, and channel length controlled by the epitaxial process rather than by lithography and ion-implantation. With epitaxial growth, it is straightforward to do bandgap engineering by incorporating films such as Si1-xGex, and/or Si1-yCy and/or Si1-x-yGexCy, into any of the aforementioned regions. Suitable band offsets at the source/channel interface  can suppress DIBL, which is a key limitation to CMOS scaling. These advantages of Vertical MOSFETs are crucial for future CMOS technology nodes, such as 22nm and below.
SD-CMOS has a metallic drain region with work-function close to the mid-gap energy of the channel material, which can be a homogenous material, a random alloy, or a superlattice. The source region has a very narrow bandgap, achievable with (Si1-yCy)m-(Si1-xGex)n superlattices, whose mid-gap level is aligned with that of the channel region, and with band offsets with the channel region that are nearly symmetric for the conduction and valence bands. The source contact is a metal with a work-function close to the mid-gap level of the source and channel regions, which in turn are aligned with the work-function of the drain. The potential barrier, for electrons and holes from the source contact to the source region, is required to be just a few KT. For operation as NMOS and PMOS with nearly symmetric threshold voltages, the work-function of the gate electrode is also aligned with the mid-gap energy level of the channel.
SD-CMOS is unique due to its band alignments: symmetric band edges, from source to drain, with respect to the mid-gap energy (the “mirror” line). Such configuration can only be obtained in the absence of doping, which if present would immediately break that symmetry. The conduction and valence band edges are required to be asymmetric with respect to a cross-section line crossing the channel through the middle of the gate.
The conduction (valence) band offset between source and channel sets the barrier height for electrons (holes) in the OFF condition for NMOS (PMOS), while applying a voltage at the gate leads to the accumulation of electrons (holes) at the source/channel interface, thereby pushing the Fermi-Level in the source above (below) the conduction (valence) band edge of the channel for the ON condition. Band diagrams and a CMOS fabrication flow for SD-CMOS will be presented.  US Patent 6,674,099  US Patent 5,914,504