Hostname: page-component-7c8c6479df-r7xzm Total loading time: 0 Render date: 2024-03-29T11:15:46.892Z Has data issue: false hasContentIssue false

Wafer Level Chip Size Packaging Technology for Bulk Acoustic Wave Filters

Published online by Cambridge University Press:  01 February 2011

Hajime Yamada
Affiliation:
ichi@murata.co.jp, Murata Manufacturing Co., Ltd., Thin Film Device Development, Research & Development Center, 1-10-1 Higashikoutari, Nagaokakyo-shi, Kyoto, N/A, Japan
Naoko Aizawa
Affiliation:
aizawa@murata.co.jp, Murata Manufacturing Co., Ltd., 1-10-1 Higashikoutari, Nagaokakyo-shi, Kyoto, N/A, Japan
Hiroyuki Fujino
Affiliation:
hirofuji@murata.co.jp, Murata Manufacturing Co., Ltd., 1-10-1 Higashikoutari, Nagaokakyo-shi, Kyoto, N/A, Japan
Yoshihiro Koshido
Affiliation:
koshido@murata.co.jp, Murata Manufacturing Co., Ltd., 1-10-1 Higashikoutari, Nagaokakyo-shi, Kyoto, N/A, Japan
Yukio Yoshino
Affiliation:
yoshino@murata.co.jp, Murata Manufacturing Co., Ltd., 1-10-1 Higashikoutari, Nagaokakyo-shi, Kyoto, N/A, Japan
Get access

Abstract

Wafer level chip size packages (WL-CSP) have been successfully fabricated for bulk acoustic wave (BAW) filters. WL-CSP has been completed at the wafer level prior to dicing. Two silicon wafers are used as a die and a lid for chip size packaging. Both device and lid wafers have the same expansion coefficient and the package is strong enough to withstand the thermal stress. The package has a hermetic seal with copper-tin intermetallic bonding. The bonded wafers are then thinned by grinding. Via holes are formed by reactive ion etching (RIE) and filled by copper electroplating. The package has solder bumps on each terminal, ready for flip-chip assembly. We have succeeded to produce CSP-BAW filters with a hermetically sealed cavity, which is 840 micrometers squared and 280 micrometers in height including solder bumps.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 Punch, M., Andrieu, B., Popin, L., Launay, N., Arnal, N., Godinat, P., Gruffat, JM., “Latest Development in DRIE for integration of passive components and Wafer-Level Packaging.”, Adixen Technical publication (2004).Google Scholar
2 Goetz, M. and Jones, C., “Chip-scale packaging techniques for RF SAW devices”, SEMI/IEEE Int’l Elect. Manuf. Tech. Symp., 27, 63 (2002).Google Scholar
3 Suzuki, N., Kinzoku Data book (in Japanese), 530, (1993).Google Scholar