Hostname: page-component-848d4c4894-nmvwc Total loading time: 0 Render date: 2024-06-20T13:15:07.406Z Has data issue: false hasContentIssue false

Using Wafer-Scale Patterns for CMP Analysis

Published online by Cambridge University Press:  14 March 2011

Brian Lee
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Terence Gan
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Duane S. Boning
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Jeffrey David
Affiliation:
Applied Materials, Santa Clara, CA
Benjamin A. Bonner
Affiliation:
Applied Materials, Santa Clara, CA
Peter McKeever
Affiliation:
Applied Materials, Santa Clara, CA
Thomas H. Osterheld
Affiliation:
Applied Materials, Santa Clara, CA
Get access

Abstract

A new set of wafer-scale patterns has been designed for analysis and modeling of key CMP effects. In particular, the goal of this work is to develop methods to characterize the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means to pattern large trenches (e.g. 1 to 15 mm wide and 15 mm tall) or circles across 4” and 8” wafers, and present oxide polish results using both stacked and solo pads in conventional polish processes. We find that large separation (15 mm) between trenches enables cleaner measurement and analysis. Examination of oxide removal in the center of the trench as a function of trench width shows a saturation at a length comparable to the planarization length extracted from earlier studies of small-scale oxide patterns. Increase in polish pressure is observed to decrease this saturation point. Such wafer scale patterns may provide information on pad flexing limits in addition to planarization length, and promise to be useful in both patterned wafer CMP modeling and studies of wafer scale CMP dependencies such as nanotopography.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Ouma, D., et al. , “An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization,” International Interconnect Technology Conference, San Francisco CA, June 1998.Google Scholar
2. Smith, T., et al. , “A CMP Model Combining Density and Time Dependencies,” CMP-MIC Conference, Santa Clara, CA, Feb. 1999.Google Scholar
3. Burke, P., et al. , MRS, Oct. 1996.Google Scholar
4. Jin, R., et al. , “A Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts,” CMP-MIC Conference, Santa Clara, CA, Feb. 1999.Google Scholar
5. Chekina, O.G., et al. , “Wear-Contact Problems and Modeling of Chemical-Mechanical Polishing,” J. Elec. Soc., Vol 145, No. 6. June 1998.10.1149/1.1838603Google Scholar
6. Yoshida, T., “Three-Dimensional Chemical-Mechanical Polishing Process Model by BEM,” ECS, Oct. 1999.Google Scholar
7. Ravi, K.V., “Wafer Flatness Requirements for Future Technologies,” Future Fab International, Issue 7, pp. 207.Google Scholar
8. Poduje, N., et al. , “Nanotopology Effects in Chemical Mechanical Polishing,” SEMI-AWG Nanotopology Workshop, Tokyo, Japan, Nov. 1999.Google Scholar