Article contents
Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress
Published online by Cambridge University Press: 25 February 2011
Abstract
Through the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.
- Type
- Research Article
- Information
- Copyright
- Copyright © Materials Research Society 1990
References
REFERENCES
- 5
- Cited by