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Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

Published online by Cambridge University Press:  25 February 2011

Tetsu Ogawa ,
Sadayoshi Hotta  and
Horoyoshi Takezawa
Tetsu Ogawa
Affiliation:
Display Technology Research Laboratory, Matsushita Electric Industrial Co., Ltd. 3–15, Yagumo-nakamachi, Moriguchi, Osaka, 570 Japan
Sadayoshi Hotta
Affiliation:
Display Technology Research Laboratory, Matsushita Electric Industrial Co., Ltd. 3–15, Yagumo-nakamachi, Moriguchi, Osaka, 570 Japan
Horoyoshi Takezawa
Affiliation:
TV-Sector, LC-Division, Matsushita Electric Industrial Co., Ltd. 26–2, Sende, Yamada, Kawakita-cho, Noh-mi-gun, Ishikawa, 923–12 Japan
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Abstract

Through the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 192: Symposium O – Amorphous Silicon Technology - 1990 , 1990 , 385
Copyright
Copyright © Materials Research Society 1990

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References

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