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Shallow Junctions for Sub-100 Nm Cmos Technology

Published online by Cambridge University Press:  21 March 2011

Veerle Meyssen ,
Peter Stolk ,
Jeroen van Zijl ,
Jurgen van Berkum ,
Willem van de Wijgert ,
Richard Lindsay ,
Charles Dachs ,
Giovanni Mannino  and
Nick Cowern
Veerle Meyssen
Affiliation:
Philips Research Laboratories, Eindhoven, THE NETHERLANDS
Peter Stolk
Affiliation:
Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, BELGIUM
Jeroen van Zijl
Affiliation:
Philips Research Laboratories, Eindhoven, THE NETHERLANDS
Jurgen van Berkum
Affiliation:
Philips CFT; Eindhoven, THE NETHERLANDS
Willem van de Wijgert
Affiliation:
Philips CFT; Eindhoven, THE NETHERLANDS
Richard Lindsay
Affiliation:
IMEC; Kapeldreef 75, B-3001 Leuven, BELGIUM
Charles Dachs
Affiliation:
Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, BELGIUM
Giovanni Mannino
Affiliation:
CNR-IMETEM, Catania, ITALY
Nick Cowern
Affiliation:
Philips Research Laboratories, Eindhoven, THE NETHERLANDS Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, BELGIUM
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Abstract

This paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 669: Symposium J – Si Front-End Processing–Physics and Technology of Dopant-Defect Interactions III , 2001 , J3.5
Copyright
Copyright © Materials Research Society 2001

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References

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