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Rapid Plan View Fabrication of Semiconductor Tem Samples for Interface Strain and Grain Size Analysis

Published online by Cambridge University Press:  21 February 2011

M. W. Cole  and
J. R. Flemish
M. W. Cole
Affiliation:
US Army, Electronics Technology and Devices Laboratory, SLCET-EP, Fort Monmouth, NJ 07703.
J. R. Flemish
Affiliation:
US Army, Electronics Technology and Devices Laboratory, SLCET-EP, Fort Monmouth, NJ 07703.
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Abstract

This study presents novel methods for chemically preparing back-side and double-side etched, plan-view TEM samples without use of jet thinning instrumentation in order to examine both surfaces and interfaces. Examples are drawn from the semiconductor industry, but this technique can be generalized for use in most materials systems. The methodology for single-sided etching consists of flat lapping and mechanical dimpling followed by material selective chemical etching to electron transparency. Interface defect analysis of heterostructures is achieved via double-sided etching to electron transparency using the proper selective chemical etchants. These techniques are presented not as replacements for conventional cross-sectional preparatory techniques, but instead, as a means for rapid sample preparation for situations where a large number of samples must be analyzed quickly, or in cases where the necessary equipment is lacking for crosssection preparation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 254: Symposium W – Specimen Preparation for Transmission Electron Microscopy of Materials III , 1991 , 233
Copyright
Copyright © Materials Research Society 1992

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