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Nanosecond Thermal Processing for Ultra-High-Speed Device Technology

Published online by Cambridge University Press:  21 February 2011

Thomas W. Sigmon ,
Anthony M. McCarthy ,
CA Kurt H. Weiner  and
Paul G. Carey
Thomas W. Sigmon
Affiliation:
Stanford University, Stanford, CA
Anthony M. McCarthy
Affiliation:
Stanford University, Stanford, CA
CA Kurt H. Weiner
Affiliation:
Lawrence Livermore National Laboratory, Livermore, CA
Paul G. Carey
Affiliation:
Siemens, Munich, FRD
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Abstract

Progress in high-speed device technology is occurring by both scaling of conventional devices, such as MOSFETs and bipolars, and the development of new device structures which take advantage of multi-layer heterostructures. As scaling in lateral dimensions allows production of devices with dimensions approaching 0.lμm, vertical scaling has become a topic of concern. In this paper we focus on nanosecond thermal processing (NTP), anew area of process technology which uses a pulsed uv-laser to perform selective doping and epitaxy on nanosecond time scales. The rapid thermal cycles and precise control of impurity profiles inherent to the new technique addresses many of the problems faced in vertical scaling for silicon MOS and bipolar structures and in the fabrication of selective heteroepitaxial layers. Following a brief historical overview and description of the process, successful applications in the fabrication of submicron MOSFETs and narrow base bipolar transistors in silicon will be presented. Structural and electrical results will be presented for heteroepitaxial layers fabricated in the GexSi1-x and InxGa1-xAs material systems by the technique.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 158: Symposium B – In-Situ Patterning: Selective Area Deposition and Etching , 1989 , 241
Copyright
Copyright © Materials Research Society 1990

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References

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