No CrossRef data available.
Article contents
Millisecond Microwave Annealing: Reaching the 32 Nm Node
Published online by Cambridge University Press: 17 March 2011
Abstract
The next generation of Si devices requires thermal treatments of 1200°C – 1300°C but can only withstand temperatures above 800°C for a few milliseconds. Current rapid thermal processing techniques cannot meet these requirements. We have designed, constructed, and tested a microwave reactor that heats Si to 1300°C in only a few milliseconds and cools the wafer at a rate that exceeds a million degrees per second. Applying millisecond microwave annealing to ultra-shallow junction formation in advanced Si devices shows that this technique meets or exceeds the thermal processing requirements for the next several generations of Si devices.
- Type
- Research Article
- Information
- Copyright
- Copyright © Materials Research Society 2004
References
REFERENCES
1.
Hu, Y.Z., Tay, S.P., “Characterization of high-K dielectric ZrO2 films annealed by rapid thermal processing,” J. Vacuum Science & Technology-B Vol. 19(5) pp. 1706–14, Sept. 2001.Google Scholar
2.
Zhao, C., Richard, O., Young, E., Bender, H., Roebben, G., Haukka, S., De-Gendt, S., Houssa, M., Carter, R., Tsai, W., VanderBiest, O., Heyns, M., “Thermo stability of amorphous zirconium aluminate high-k Layers,” Journal of Non-Crystalline Solids, Vol. 303(1) pp. 144–9, May 2002.Google Scholar
3.
Lee, P.F., Wong, K.H., Chan, H.L.W., Choy, C.L., “Epitaxial growth of yttrium- stabilized HfO2 high-k gate dielectric thin films on Si,” J. Appl. Phys, Vol. 94(2) pp. 912–15, July 2003.Google Scholar
4.
Cho, M., Park, H.B., Park, J., Hwang, C.S., Lee, J.C., Oh, S.J., Jeong, J., Hyun, K.S., Kang, H.S., Kim, Y.W., Lee, J.H., “Thermal annealing effects on the structural and electrical properties of HfO2/Al2O3 gate dielectric stacks grown by atomic layer deposition on Si substrates,” J. Appl. Phys., Vol. 94(4) pp. 2563–71, Aug 2003.Google Scholar
5. International Technology Roadmap for Semiconductors, published by the Semiconductor Industry Association and found at http://www.itrs.net.Google Scholar
6.
Lerch, W., Bayha, B., Downey, D.F., Arevalo, E.A., “State of the art techniques for ultra- shallow junction formation,” in Proc. of the 199th meeting of the Electrochemical Society: Rapid Thermal and Other Short-Time Processing Technologies II, pp. 321–6, 25 March 2001.Google Scholar
7.
Thompson, K., Booske, J.H., Gianchandani, Y.B., Cooper, R.F., “Electromagnetic annealing for the 100 nm node,” Electron Device Lett, vol. 23 (3), pp. 127–9, March 2002.Google Scholar
8.
Ross, J., McCoy, S., Elliott, K., Gelpey, J., Downey, D.F., Arevalo, E.A., “Characterizing Implant Behavior During Flash RTP by Means of backside diagnostics,” presented at the 10th International Conference on Advanced Thermal Processing of Semiconductors – RTP 2002, Vancouver, Canada, p. 99–105.Google Scholar
9.
Gelpey, J., Elliott, K., Camm, D., McCoy, S., Ross, J., Downey, D. F., Arevalo, E. A., “Advanced Annealing for Sub-130nm Junction Formation,” in Rapid Thermal and Other Short-Time Processing Technologies III, presented at the 201st meeting of the electrochemical society and published in the proceedings. p. 2002–11 (May 2002).Google Scholar
12.
Liebert, R.B.
et al. , Proc. of the 13th International conference on Ion Implant Technology, 472–5 (2000).Google Scholar