Using a leakage-compensated charge (LCCV) technique to obtain static capacitance-voltage (C-V) curves, we extend the standard high-low C-V method for determining the interface state level density, Dit as a function of energy in the silicon band gap to metal-oxide-silicon capacitors in the direct tunneling regime (oxide thickness ∼<3.5 nm). The LCCV technique yields true static C-V curves for oxides at least as thin as 2.8 nm, where the tunnel leakage current is so high that the usual quasistatic C-V measurement is not possible. As applications of this method, Dit is compared for fresh oxides of different tunnel thickness, and Dit is measured before and after constant voltage stress of a 3.5-nm oxide. The stress results indicate, as in other work on thicker oxides, that interface traps are created during the stress, with peak densities both below and above midgap. This approach is expected to be useful for evaluating both ultra-thin oxides and leaky alternate gate dielectrics.