Hostname: page-component-7bb8b95d7b-nptnm Total loading time: 0 Render date: 2024-09-22T18:13:05.141Z Has data issue: false hasContentIssue false
  • English
  • Français

Manufacturing Considerations for VLSI Interconnect Systems

Published online by Cambridge University Press:  25 February 2011

Michael E. Thomas
Michael E. Thomas*
Affiliation:
National Semiconductor Corporation, Fairchild Research Center, 2900 Semiconductor Dr., MS E-100, Santa Clara, CA 95052
Get access

Abstract

In the next decade, it is expected that integrated circuits having 5 to 7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 meters/cm2/level. Multilevel interconnect technology needs are presently generating processing and structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials, and electrical requirements which must be addressed by the interconnect engineer. A comparison of interconnect systems based on different conductor materials will be presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 337: Symposium B – Advanced Metallization for Devices and Circuits—Science, Technology and Manufacturing III , 1994 , 13
Copyright
Copyright © Materials Research Society 1994

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 Renteln, P., Thomas, M.E. and Pierce, J.M., “Characterization of Mechanical Planarization Processes”, V-MIC Conf. (1990) 57.Google Scholar
2 Thomas, M.E., Sekigahama, S., Renteln, P. and Pierce, J.M., “ The Mechanical Planarization oflnterlevel Dielectrics for Multilevel Interconnect Applications”, V-MIC Conf. (1990) 438.Google Scholar
3 Maly, W. and Deszczka, J., “Yield Estimation Model for VLSI Artwork Evaluation”, Electronics Letters, Vol. 19, no.6, (Mar 1993) 226 Google Scholar
4 Stapper, C.H., “Integrated Circuit Yield Statistics”, Proc. of IEEE, 71(4), 453.Google Scholar
5 Khare, J., Daniels, B., Campbell, D., Thomas, M.E. and Maly, W., “ Extraction of Defect Characteristics for Yield Estimation Using the Douvle Bridge Test Structure”, Intern, Sympos. on VLSI Tech, Systems, and Applications, Taipei, Taiwan, May (1991) 424.Google Scholar
6 Maly, W. , “ Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits”, IEEE Transactions on CAD, (July 1985) 161.Google Scholar
7 Ferris-Prabhu, A.V., “Modeling of Critical Area in Yield Forecasts”, IEEE Journal of Solid State Circuits, SC-20, no.4, (August 1985) 874.Google Scholar
8 Luther, B. et al. , “ Planar Cu-Polyimide Back end of the Line Interconnections for ULSI Devices”, V-MIC Conf. (1993) 15.Google Scholar
9 Saadat, I.A. and Thomas, M.E., “VLSI Interconnect Options for On-Chip High Performance Applications”, Wescon, Nov. (1991) 318.Google Scholar
10 Thomas, M.E., Saadat, I.A. and Sekigahama, S., “VLSI Multilevel Micro-Coaxial Interconnects for High Speed Devices”, IEDM Dec. (1990) 3.5.1.Google Scholar