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Fabrication and Electronic Characteristics of Silicon Nanowire MOSFETs

Published online by Cambridge University Press:  01 February 2011

Hironori Yoshioka
Affiliation:
yoshioka@semicon.kuee.kyoto-u.ac.jp, Kyoto University, Department of Electronic Science and Engineering, Kyotodaigaku-katsura, Nishikyo, Kyoto, 615-8510, Japan, +81-75-383-2302, +81-75-383-2303
Yuichiro Nanen
Affiliation:
nanen@semicon.kuee.kyoto-u.ac.jp, Kyoto University, Department of Electronic Science and Engineering, Kyotodaigaku-katsura, Nishikyo, Kyoto, 615-8510, Japan
Jun Suda
Affiliation:
suda@kuee.kyoto-u.ac.jp, Kyoto University, Department of Electronic Science and Engineering, Kyotodaigaku-katsura, Nishikyo, Kyoto, 615-8510, Japan
Tsunenobu Kimoto
Affiliation:
kimoto@kuee.kyoto-u.ac.jp, Kyoto University, Department of Electronic Science and Engineering, Kyotodaigaku-katsura, Nishikyo, Kyoto, 615-8510, Japan
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Abstract

The n-type silicon nanowire MOSFETs with a nanowire shape being triangular or trapezoidal, have been fabricated on SOI substrates and characterized. The height and bottom-width of the triangular nanowire has been 10 nm and 19 nm, respectively. The devices have shown good gate control, such as a nearly ideal subthreshold slope of 63 mV/decade, high Ion/Ioff ratio of 107, and small drain-induced barrier lowering of 5 mV/V at room temperature. The low field mobility of triangular nanowire has been estimated to be 130 cm2/V·s and shown no difference with the change of the nanowire shape and direction within the investigated range.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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