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Effects of Post-Deposition Annealing Temperature on Band Alignment and Electrical Characteristics of Lanthanum Cerium Oxide on 4H-SiC

Published online by Cambridge University Press:  13 June 2012

Way F. Lim
Affiliation:
Energy Efficient & Sustainable Semiconductor Research Group, School of Materials & Mineral Resources Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia
Kuan Y. Cheong
Affiliation:
Energy Efficient & Sustainable Semiconductor Research Group, School of Materials & Mineral Resources Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia
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Abstract

Investigation of lanthanum cerium oxide as a gate oxide on 4H-SiC was performed by varying post-deposition annealing temperature from 400 to 1000°C. Energy band alignment and band gap of bulk oxide and interfacial layer (IL) with respect to SiC were extracted using X-ray photoelectron microscopy. Two band alignment structures were proposed and the change of band alignment was affected by the changes in chemical composition in bulk oxide and in IL that may induce lattice strains and dipoles. A conduction band offset of IL/SiC was 0.97 eV for sample annealed at 1000°C, which was comparable to the value extracted from Fowler-Nordheim model. The acquisition of sufficient conduction band offset, coupled with the lowest slow trap density, effective oxide charges, interface trap density, as well as total interface trap density, yielded the lowest leakage current density for this sample.

Type
Research Article
Copyright
Copyright © Materials Research Society 2012

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References

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