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Detecting Impurities in the Ultra Thin Silicon Oxide Layer By Hg-Schottky Capacitance–Voltage (CV) Method

Published online by Cambridge University Press:  21 March 2011

D. Liu ,
Q. Wang ,
H. Paravi ,
V. Drobny  and
J. Moquin
D. Liu
Affiliation:
Texas Instruments Inc.,Tucson, AZ 85706
Q. Wang
Affiliation:
Fairchild Semiconductor,West Jordan, UT 85088
H. Paravi
Affiliation:
Fairchild Semiconductor,West Jordan, UT 85088
V. Drobny
Affiliation:
Texas Instruments Inc.,Tucson, AZ 85706
J. Moquin
Affiliation:
Texas Instruments Inc.,Tucson, AZ 85706
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Abstract

Detecting impurities or contaminations in the ultra thin silicon oxide layer is one of the most serious challenges in wafer processing as device is scaled down toward deep sub-micron. These impurities or contaminations will create charge traps in the oxide layer and degrade gate oxide integrity (GOI). The MOS Capacitance-Voltage method which has been used to study the electrical charges in relative thicker oxide layer (> 5 nm) cannot detect, however, these contaminations related charges in the ultra thin silicon oxide layer. In this article, a new method has been developed to determine the electrical charges associated with the contaminations in an ultra thin oxide layer using Hg-Schottky capacitance-voltage method. The oxide layers of 1.2 nm in thickness with and without Cu-contamination have been tested with this new method. The results show that the new method can be used to qualitatively identify the electrical charges trapped in the ultra thin silicon oxide layer and the trapping levels associated with the contamination. The interactions among sub-stochiometric oxide structure and electron traps introduced by the metal impurities have been discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 670: Symposium K – Gate Stack and Sillicide Issues in Silicon , 2001 , K7.7
Copyright
Copyright © Materials Research Society 2001

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References

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