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Conductivity Enhancement in Thin Silicon-on-Insulator Layer Embedding Artificial Dislocation Network

Published online by Cambridge University Press:  01 February 2011

Yasuhiko Ishikawa
Affiliation:
Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Hamamatsu 432-8011, Japan
Kazuaki Yamauchi
Affiliation:
Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Hamamatsu 432-8011, Japan
Chihiro Yamamoto
Affiliation:
Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Hamamatsu 432-8011, Japan
Michiharu Tabe
Affiliation:
Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Hamamatsu 432-8011, Japan
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Abstract

A nanometer-scale dislocation network is artificially formed in thin top Si layer of silicon-on-insulator (SOI) structure, and effect of the dislocation network on the transport property is examined from the viewpoint of nanodevice applications. The artificial network of screw dislocations was formed in the Si layer using a wafer bonding of a pair of (001) SOI wafers with a slight misalignment of the in-plane crystalline directions to cause a lattice mismatch. The transmission electron microscopy clearly revealed the formation of dislocation network at the bonding interface with the period less than ∼20 nm. The dislocation network was found to enhance the conductivity in the Si bicrystal layer more than one order of magnitude in comparison with that in the monocrystal layer free from the dislocations. The enhanced conductivity is probably derived from an increased concentration of electrons around the dislocations due to the formation of donor-like gap states.

Type
Research Article
Copyright
Copyright © Materials Research Society 2005

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