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A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces

Published online by Cambridge University Press:  11 February 2011

Antonio C. Oliver  and
Jack M. Blakely
Antonio C. Oliver
Affiliation:
Materials Science & Engineering, Cornell University, Ithaca, NY 14850, U.S.A.
Jack M. Blakely
Affiliation:
Materials Science & Engineering, Cornell University, Ithaca, NY 14850, U.S.A.
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Abstract

Surface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 747: Symposia T/V – Crystalline Oxides on Semiconductors – Interfacial Issues for Oxide-Based Electronics , 2002 , V4.6
Copyright
Copyright © Materials Research Society 2003

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References

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