Junctions were formed in thin SiGe/strained Si substrates with a thickness of 250-350 nm to assess the effect of different buffer layer parameters (bandgap, dislocations, thickness) on the junction leakage density that can be expected in MOSFET devices. The implantations used are standard well, channel and Highly Doped Drain (HDD) implants. Both p+/n and n+/p junctions were evaluated. The total thickness of the buffer layers was varied to compare the effect of different structural layers on the diode leakage. This investigation shows that the effect of an increased defect density is dominant at room temperature for the strained Si samples, resulting in 4-5 orders of magnitude increase in leakage. However, there is a different gradation in leakage dependence for thick and thin buffer layers, especially at higher temperatures.