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Very low off Current Behavior in high Performance a-Si:H TFT

Published online by Cambridge University Press:  15 February 2011

Jung-Kee Yoon ,
Woong-Sik Choi ,
Yong-Ho Jang  and
Seong-Mo Seo
Jung-Kee Yoon
Affiliation:
LCD Research Lab., LG Electronics Inc. (Goldstar), Hogae-Dong 533, Anyang-Shi, Kyongki-Do, 430–080, Korea
Woong-Sik Choi
Affiliation:
LCD Research Lab., LG Electronics Inc. (Goldstar), Hogae-Dong 533, Anyang-Shi, Kyongki-Do, 430–080, Korea
Yong-Ho Jang
Affiliation:
LCD Research Lab., LG Electronics Inc. (Goldstar), Hogae-Dong 533, Anyang-Shi, Kyongki-Do, 430–080, Korea
Seong-Mo Seo
Affiliation:
LCD Research Lab., LG Electronics Inc. (Goldstar), Hogae-Dong 533, Anyang-Shi, Kyongki-Do, 430–080, Korea
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Abstract

The off currents in high performance a-Si:H TFT's were measured below 10−12 A. The Ioff-Vgs behavior is similar to that of a poly-Si TFT, in which the current increases rapidly with negative gate bias under a large drain bias while it stays almost constant under a small drain voltage. It seems the thermally-assisted tunneling via localized states occurs near the drain region as in the case of poly-Si TFT, although the current level is quite different. The off current change after negative bias stress at room temperature can be explained by the defect creation, but defects can be reduced by negative stress at 180 °C according to the defect pool model.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 377: Symposium A – Amorphous Silicon Technology 1995 , 1995 , 743
Copyright
Copyright © Materials Research Society 1995

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References

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