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A Two-Step Spacer Etch for High-Aspect-Ratio Gate Stack Process

Published online by Cambridge University Press:  14 March 2011

Chien Yu
Affiliation:
IBM Microelectronics, Semiconductor Research & Development Center, East Fishkill, NY 12533
Rich Wise
Affiliation:
DRAM Development Alliance IBM/Infineon
Anthony Domenicucci
Affiliation:
IBM Microelectronics, Semiconductor Research & Development Center, East Fishkill, NY 12533
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Abstract

A highly selective nitride etch was developed for gate stack spacer process in advanced memory programs. Based on methyl fluoride chemistry with better than 8:1 selectivity of nitride:oxide, this process exhibits minimal erosion to the underlying RTO thermal oxide for consistent diffusion ion-implant control. As the groundrule changed to 0.175um and below, a two-step etch scheme was employed to maintain the profile control in high-aspect-ratio structures. The stability and repeatability of the process is demonstrated in the SPC chart of the post etch FTA site measurement.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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