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Top Gate Tft for Large Area Electronics

Published online by Cambridge University Press:  17 March 2011

Mark Meitine
Electrical and Computer Engineering Department, University of Waterloo 200 University Avenue West, Waterloo, Ontario N2L 3G1, Canada
Andrei Sazonov
Electrical and Computer Engineering Department, University of Waterloo 200 University Avenue West, Waterloo, Ontario N2L 3G1, Canada
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The TFT fabrication by PECVD at low processing temperature (<100°C) is of great importance due to its compatibility with low-cost plastic foil substrates. The first bottom gate amorphous silicon TFTs fabricated at 75°C in our lab demonstrated the leakage current of 10−12A, the threshold voltage of 15V and the field effect mobility of 10−2cm2/(Vs). To increase the field-effect mobility, reduce the threshold voltage, and reduce the mask count, nanocrystalline silicon based top gate TFT was designed.

The TFT fabrication process was done at maximum processing temperature of 75°C. The direct PECVD SiNx and SiOx/SiNx stack were used as gate dielectrics. Nanocrystalline silicon was used as the channel layer. The SiNx gate dielectric TFTs demonstrated the leakage current about 10−13A, the threshold voltage of 8..10V, the field effect mobility of ∼10−4cm2/(Vs), the subthreshold slope of 4..8V/decade, and Ion/Ioffratio of about 102. High source and drain contact resistance were attributed to low efficiency of phosphorous doping in amorphous silicon at 75°C, which also limited the Ion value. Using n+ nc-Si for the source and drain contacts, the Ion/Ioffratio was increased to 106, and the field effect mobility was increased to ∼0.1cm2/(Vs). The threshold voltage, however, increased, which was attributed to higher fixed charge.

Research Article
Copyright © Materials Research Society 2004

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