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A Study on Selective Etching of SiGe Layers in SiGe/Si Systems for Device Applications

Published online by Cambridge University Press:  01 February 2011

Takashi Yamazaki
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Tomohide Sekikawa
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Shinya Morita
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Yoshitaka Hakamada
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Hiroyuki Ohri
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Shun-ichiro Ohmi
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
Tetsushi Sakai
Affiliation:
Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226–8502, Japan
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Abstract

Selective etching of a SiGe layer for Si/SiGe/Si stacked layers was investigated for device applications. The SiGe layer is selectively and laterally etched by a HF:HNO3:H2O solution after patterning the layers. The selective etching rate of the SiGe layer increased as the Ge ratio increased. The etching rate of a SiGe layer annealed at 800°C did not change from an as-grown sample, and the Ge diffusion into Si was very small. However, the etching rate of a layer annealed at 1000°C was found to have decreased, and Ge diffused into Si in large amounts. This indicates that annealing at less than 800°C is suitable for device applications.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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References

[1] Guarini, K. W. et al., IEDM Tech. Dig., 425 (2001).Google Scholar
[2] Hergenrother, J. M. et al., IEDM Tech. Dig., 75 (1999).Google Scholar
[3] Hisamoto, Digh et al., IEEE Trans. Electron Devices, vol. 47, 2320 (2000).Google Scholar
[4] Sakai, T., Ohmi, S., Sasaki, D., Sakuraba, M., and Murota, J., International SiGe Technology and Device Meeting, Meeting Abstract, 31, January (2003).Google Scholar
[5] Murota, J., and Ono, S., Jpn. J. Appl. Phys., Part 1, No. 4B, 2290 (1994).CrossRefGoogle Scholar
[6] Godbey, D. J. et al., J. Electrochem. Soc., Vol. 139, No. 10, 2943 (1992).CrossRefGoogle Scholar

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