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SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge-Condensation Technique for High-Mobility Channel CMOS Devices

Published online by Cambridge University Press:  17 March 2011

Tsutomu Tezuka
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Tomohisa Mizuno
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Naoharu Sugiyama
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Shu Nakaharai
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Yoshihiko Moriyama
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Koji Usuda
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Toshinori Numata
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Norio Hirashita
Affiliation:
MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan
Tatsuro Maeda
Affiliation:
MIRAI-AIST, Chuuou-dai-4, Higashi 1-1-1, Tsukuba, 305-8562, Japan
Shin-ichi Takagi
Affiliation:
MIRAI-AIST, Chuuou-dai-4, Higashi 1-1-1, Tsukuba, 305-8562, Japan
Yoshiji Miyamura
Affiliation:
Komatsu Electronic Metals, 3-25-1, Shinomiya, Hiratsuka, Kanagawa,, Japan
Eiji Toyoda
Affiliation:
Toshiba Ceramics, Nishi-Shinjuku Kimuraya Bldg., 7-5-25, Nishi-Shinjuku, Tokyo, Japan
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Abstract

A new fabrication method of SiGe-on-Insulator (SGOI) and Ge-on-Insulator (GOI) structures are presented as well as the application to high-mobility channel CMOS devices. This method, the Ge-condensation technique, consists of epitaxial growth of a SiGe layer with a low Ge fraction on an SOI substrate and successive oxidation at high temperatures, which can be incorporated in conventional CMOS processes. During the oxidation, Ge atoms are pushed out from the oxide layer and condensed in the remaining SiGe layer. The interface between the Si and SiGe layers is disappeared due to the interdiffusion of Si and Ge atoms. Eventually, an SGOI layer with a higher Ge fraction is formed on the buried oxide layer. The Ge fraction in the SGOI layer can be controlled by the oxidation time because total amount of Ge atoms in the SGOI layer is conserved throughout the oxidation process. We found that the lattice relaxation in the SGOI layer also can be controlled through the initial SiGe thickness. P- and n-type strained SOI MOSFETs, which were fabricated on relaxed SGOI substrates formed by this technique, exhibited mobility enhancement of 50% and 80%, respectively. CMOS ring oscillators comprised of the MOSFETs exhibited reduction in propagation delay of 70%-30% compared to a conventional SOI-CMOS device. Ultrathin-body strained SGOI pMOSFETs with high Ge fraction and surface channels were also fabricated by this technique. These devices exhibited hole-mobility enhancement factors up to 2.3. Furthermore, Ge-on-Insulator (GOI) structures with thicknesses less than 10 nm were realized for ultrathin body GOI-CMOS applications by using the Ge-condensation technique. In conclusion, the Ge-condensation technique is a promising technique for fabricating various types of high-mobility channel-on-insulator devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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