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Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate

Published online by Cambridge University Press:  01 February 2011

Jaehyun Moon
Affiliation:
jmoon@etri.re.kr, Electronics and Telecommunications Research Institute, Basic Research Lab., 161 Gajeong-Dong, Yuseong-Gu, Daejeon, N/A, 305-350, Korea, Republic of
Dong-Jin Park
Affiliation:
jins1130@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
Choong-Heui Chung
Affiliation:
choong@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
Yong-Hae Kim
Affiliation:
yhakim@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
Sun Jin Yun
Affiliation:
sjyun@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
Jung Wook Lim
Affiliation:
limjw@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
Jin Ho Lee
Affiliation:
leejinho@etri.re.kr, Electronics and Telecommunications Research Institute, Daejeon, N/A, 305-350, Korea, Republic of
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Abstract

Compared to plastic, from the view point of ultra low temperature poly-Si (ULTPS) processes for realizing flexible active matrix organic light emitting diode (AM-OLED) display, SSF offers high thermal resistance and chemical stability, and lithography stability. As SSF is stiffer than plastic film, SSF is expected to reduce stress which originates from difference in coefficient of thermal expansion. However, SSF substrate itself also bears surface roughness problem, which necessitates an appropriate planarization step. Also to fully integrate both the drive circuits and the pixel thin-film transistor(TFT)s in a monolithic complementary metal-oxide-semiconductor (CMOS) technology high mobility is required, calling for poly-Si usage.

We will deal with the planarization process, and then address various processing issues. Especially, we will demonstrate our successful SLS of Si on SSF substrates. Finally we show the device performances. All fabrication temperatures were kept below 200 oC to meet a ULTPS process.

Due to the rolling process for manufacturing foils, the SSF surface is rough. We have measured average roughness of 500 nm, respectively. With benzocyclobutene (BCB), we have successfully planarized the surface with average roughness was less than 0.5 nm.

Our TFT's active layer was obtained by laser crystallizing amorphous Si (a-Si) films. To obtain a high quality gate dielectric film, we formed a SiO2 film using an O2 plasma treatment on the surface of the poly-Si film and then deposited Al2O3 film by plasma enhanced atomic layer deposition. Then gate metal was deposited and patterned. Source and drain regions were p+ doped by ion implantation to form a self-aligned gate structure. We have used SiNx film as interlayer dielectrics.

Briefly we discuss a practical approach for realizing SLS on a SiO2 buffer. The Si-on-SiO2 layer stacking is energetically unstable. Should have not controlled the heat during laser crystallization, liquid Si would recede to expose the SiO2 layer. Dewetting is suppressed by adjusting the buffer density, and densifying the a-Si film. To implement the SLS, we have optimally conjugated the densities of the buffer film and the a-Si film to produce Si grains with sizes of ~6 ¥ìm on a BCB planarized SSF.

Our p-channel TFT transfer performance exhibits a field effect mobility (¥ì) of 95 cm2/Vs, a threshold voltage (Vt) of -3 V and a sub-threshold swing(S-S) of 0.5 V/dec.. The off-current level is ~ 10 pA at drain voltage (Vd) of -1V and the Ion/Ioff is 106 . Especially our stable Vt consents to the electrical stability for driving displays. This feature might be attributed to the improved interface between the active layer and the gate dielectrics by plasma oxidation.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate
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Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate
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