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Schottky-Barrier Si Nanowire MOSFET: Effects of Source/Drain Metals and Gate Dielectrics

Published online by Cambridge University Press:  01 February 2011

Weifeng Yang
Affiliation:
g0500110@nus.edu.sg, SNDL, ECE department, Block E4A #02-04 Engineering Drive 3, Singapore 117576, Singapore, 117576, Singapore
Sungjin Whang
Affiliation:
g0306273@nus.edu.sg, Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore
Sungjoo Lee
Affiliation:
elelsj@nus.edu.sg, Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore
Haichen Zhu
Affiliation:
haichen_zhu@nus.edu.sg, Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore
Hanlu Gu
Affiliation:
g0503568@nus.edu.sg, Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore
Byungjin Cho
Affiliation:
elebjcho@nus.edu.sg, Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore
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Abstract

We fabricated and studied the performance of Schottky-Barrier Si nanowire FETs (SiNW FET) by using Vapor-liquid-solid (VLS) grown Au-catalyzed SiNWs (20 nm). These devices were formed on various gate dielectrics (HfO2 or Al2O3) with different metal Source and Drain (S/D) regions (Pd, Ni). P-type behavior was observed and high Ion/Ioff ratio (~105) was achieved from undoped SiNW FETs. Besides, no ambipolar transportation was observed in our devices performance. This is possibly due to the small schottky barrier height for hole carriers at Source sides formed by high work-function metal. Furthermore, low subthreshold slope as 68mV/decade was obtained from SiNW FETs integrated with Ni S/D and Al2O3 High-¦gate dielectric.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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